JPS6132757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory testing device that tests a memory under test by accessing the memory under test using an address from a pattern generator and comparing the read data with an expected value pattern.

In a memory test, one test sequence is completed by repeatedly accessing each part of the memory under test using a walking method, a gearing method, or the like. Conventional memory test equipment not only detects whether the memory under test is good or defective, but also analyzes the memory under test during the test sequence in order to analyze the cause of the failure of the memory under test. Store the data read from the memory, the address and/or expected value at the time of failure occurrence, or use mask data to mask the test results for a specific address of the memory under test during the test, Furthermore, when testing a read-only memory, it may be difficult to logically generate an expected value pattern using a pattern generator. This expected value pattern is compared with the data read from the memory under test.

From this point of view, memory test equipment has generally been provided with a readable/writable storage device. Conventionally, only one readable/writable storage device is provided, and while a test is being performed on this single readable/writable storage device, only the data read from the memory under test is stored in the memory under test. The mask data or the expected value pattern may be used only to store the address where the failure occurred, or only the mask data or the expected value pattern may be stored in advance in that single read/write storage device, and only the mask data or the expected value pattern may be used for test execution. Only the value pattern was being read.
However, if there is a request to store defective addresses while generating a mask pattern, a storage device for storing the mask pattern in advance and a storage device for storing detected defective addresses are required. In order to satisfy not only this request but also various usage requests for the above-mentioned read/write storage device, a large number of storage units are required.

An object of the present invention is to provide a memory testing device that is equipped with two storage units and can be used flexibly to effectively perform various functions, and can therefore be used efficiently. It's about doing.

According to this invention, the address from the pattern generator is delayed by the delay circuit, and the first selector selects the direct output of the pattern generator or the output of the delay circuit to access the first storage section, Similarly, the second selector selects the output of either the pattern generator or the delay circuit to access the second storage section. Furthermore, the outputs of these first and second storage sections are stored in a third storage section.
Select by a selector, or take out both of them and supply them to a comparison section to compare with the readout output of the memory under test, or set a mask at that time, that is, a mask so that the test is ignored for that certain address. conduct. When a defective pattern such as a mismatch occurs from the output of the comparator circuit, it is supplied to the write control section as necessary, thereby controlling the write to the first storage section, the second storage section, or both.

In this way, for example, mask data for the same address is generated in one storage section, and a defective address is stored in the other storage section. Although there is a considerable time difference between generating mask data for the same address and storing the defective address, this can be easily done by selecting the first and second selectors.

Next, a memory testing device according to the present invention will be explained with reference to the drawings. FIG. 1 shows the concept of an example of a memory test device, in which a terminal 12 of a pattern generator 11
The next address accesses the memory under test 13, and when the memory under test 13 is controlled to write state, the data from the terminal 14 of the pattern generator 11 is written to the memory under test 13, and the memory under test 13 When the memory under test 13 is controlled to be in the read state, the memory under test 13 is read by the access, and the corresponding bits of the read/write output and the expected value pattern from the terminal 15 of the pattern generator 11 are compared in the comparison circuit 16. Ru. If a mismatch is detected in the comparison, an output indicating a defect is generated at the terminal 17, and the memory under test 13 is determined to be a defective product. Although not shown in the figure, the memory under test 13
The pattern generator 11 controls reading and writing of the data.

A readable/writable storage device 18 is provided to not only test whether the memory under test 13 is a defective product but also to analyze the cause of the failure if the memory under test 13 is a defective product. This can be accessed using the address of the terminal 12, and the output of the terminal 17 can be stored in the storage device 18 as a so-called defective address when a defect occurs, for example, as shown by the dotted line _l1 , or the expected value pattern at that time can be stored. Memorization as shown by dotted line l ₂ is performed during the test sequence. Furthermore, during the test sequence, failure analysis can be performed by performing a test while applying a so-called mask that ignores the test results for a certain address, a certain area part, or a specific bit in the address of the memory under test 13. Efforts are made to make the test easier or to shorten the test time.

In this case, mask data is stored in the storage device 18 in advance before the start of the test, and during the test, it is read out using the address from the pattern generator 11, and the read mask data is shown by the dotted line _l3 . The signal is supplied to the comparator circuit 16 to perform necessary masking. Furthermore, if the memory under test 13 is a read-only memory, for example, it is difficult to create the expected value pattern using the pattern generator 11, so it is necessary to store the expected value pattern in advance in the storage device 18 before starting the test. During the test, the memory device 18 is read out using the address from the pattern generator 11, and the read expected value pattern is compared with the output of the memory under test 13, as shown by the dotted line _l4 . It will be done.

The present invention provides two storage sections for storing various data, generating data, etc., and makes effective use of these sections to exhibit many functions. For example, FIG. 2 shows a main part of an example of the present invention. Terminal 12 of pattern generator 11
The second address is also supplied to the delay circuit 21, and the delayed address from the delay circuit 21 and the direct address from the pattern generator 11 are selected by the first selector 22 and used as the address for accessing the first storage section 23. Given. One of the address of the terminal 12 and the delay address of the delay circuit 21 is selected by the second selector 24 and given as an address for accessing the second storage section 25. These are the first storage section 23 or the second storage section 25
The readout output is selected by the third selector 26 and supplied to the expected value data input terminal 27 of the comparison circuit 16, and is also supplied to the second storage section 25 or the first storage section 2.
The readout output of 3 is supplied to the mask data input terminal 28. Data indicating a mismatch from the output terminal 17 of the comparison circuit 16 is applied to a write control circuit 29, and the control circuit 29 is configured to be able to apply a write command to at least one of the storage units 23 and 25.

Although not shown in the figure, the first and second selectors 22, 2
4 is, for example, a well-known multiplexer, each of which is connected to a control line, and selectively outputs one of the two input addresses in response to a selection control signal applied to the control line. The third selector 26 also consists of a combination of an AND circuit and an OR circuit, and one of the two input data is sent to the terminal 2 by a selection control signal applied to a control line (not shown).
7, 28, or two input data are supplied to terminals 27, 28, respectively. A control line (not shown) is also connected to the control circuit 29, and one input thereof is supplied to at least one of the two output sides in accordance with a selection control signal applied to the control line.

For example, to explain an example in which mask data is generated and a defective address is stored, mask data is stored in advance in the first storage section 23 before the start of a test, and the first selector 22 is connected to a terminal of the pattern generator 11. The first selector 22 selects the 12 addresses directly, that is, without delay.
is set, and the second selector 24 is set to select the output of the delay circuit 21. Third selector 26
In this case, the output of the first storage section 23 is supplied to the mask data input terminal 28, and the output of neither of the storage sections 23 and 25 is supplied to the expected value data input terminal 27. Write control section 29
is set to give a write command to the second storage unit 25. In other words, the connection state shown by the thin line in FIG. 2 is established.

Start the test in this state. As explained with reference to FIG. 1, the memory under test 13 is read by the address of the terminal 12, and the read output
The comparison circuit 16 compares the expected value data given through 5 and 27. At the same time, the first storage section 23 is simultaneously accessed by the address generated by the pattern generator 11. Therefore, when the memory under test 13 is accessed, the first storage section 23 is simultaneously accessed and mask data is applied to the terminal 28, and necessary masking is performed, that is, the bits or addresses specified by the mask data or the memory under test are accessed. The test results for specific areas of the test are ignored.

When a mismatch is detected in the comparison circuit 16,
A write command is given to the second storage unit 25 through the write control unit 29 . At this time, the delay circuit 21
Data indicating a defect with respect to the supplied address is stored in the storage unit 25 through a write data line (not shown), and a so-called defective address is stored. The storage unit 25 is accessed using the address at the time of occurrence of the defect, and "1" is stored at the address location. In other words, in general, the time when the comparison result of the output of the memory under test 13 appears from the comparison circuit 16 is delayed with respect to the generation of the address generated when accessing the memory under test 13, that is, the address of the terminal 12, and the delay is several cycles. It may become. The address is delayed by the delay circuit 21 by the amount of delay, and this delayed address is applied to the storage section 25 through the second selector 24 to access the storage section 25. Therefore, the storage section 25 is accessed at the same address as the address at which the memory under test 13 is accessed, and data indicating a defect, for example "1", is stored at that location.

Although the supply of various types of data to be stored to the storage units 23 and 25 is omitted in the figure, it goes without saying that data can be supplied and stored as necessary through the write data line. In other words, the above-mentioned mask data and the expected value pattern when the memory under test 13 is a read-only memory are stored in the storage sections 23 and 25 through the write data line.

The use of the storage units 23 and 25 is not limited to the above example; for example, mask data may be stored in the storage unit 23, and expected value patterns may be stored in the storage unit 25, respectively, and when the memory under test 13 is a read-only memory, this may be stored at the terminal 12. At the same time, the expected value pattern stored in the storage unit 25 is read out,
This is applied to the comparator circuit 16 through the terminal 27 for testing. In this case, as shown by dotted lines in FIG. 2, selectors 22 and 24 both select the address of terminal 12, and selector 26 supplies the output of storage section 23 to terminal 28 and the output of storage section 25 to terminal 27. The write control section 29 writes the storage section 23,
25 so that no write command is given during the test, the mask data is stored in advance in the storage section 23 and the expected value pattern is stored in the storage section 25, and then the test is started.

The defective address is stored in the storage unit 23, and the storage unit 2
When reading the expected value pattern from 5, the storage unit 2
5 stores the expected value pattern in advance, selects the output address of the delay circuit 21 with the selector 22,
The selector 24 selects the address of the terminal 12, the selector 26 supplies the output of the storage section 25 to the terminal 27, the output of neither of the storage sections 23 and 25 is supplied to the terminal 28, and the write control section 29 After each setting is made to give a write command to section 23,
Start the exam.

When storing a defective address in the memory section 23 and an expected value pattern at the time of occurrence of a defect in the memory section 25, the selectors 22 and 24 select the delay circuit 2, respectively.
1 output address is selected, the selector 26 does not supply any of the outputs of the storage units 23 and 25 to the terminals 27 and 28, and the write control unit 29 selects the output address of the storage units 23 and 25.
A write command can be given to each of
After applying the expected value pattern of the terminal 15 to the write data line of the storage section 25, the test may be started.

For example, after a defective address is stored in the storage unit 23 in a certain test sequence, the defective address can be used as mask data in the next test sequence. In this case, after the test sequence for storing the defective address in the memory section 23 is completed, the selector 22 selects the address of the terminal 12, and the selector 26 supplies the output of the memory section 23 to the terminal 28 before starting the next test. Just start the sequence.

As described above, according to the present invention, the storage section 2
3.25 can be used very effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general configuration of a memory testing device, and FIG. 2 is a block diagram showing the main parts of the memory testing device according to the present invention. 11: Pattern generator, 12: Address output terminal, 13: Memory under test, 15: First pattern output terminal, 16: Comparison circuit, 17: Mismatch output terminal, 21: Delay circuit, 22: First selector, 2
3: first storage section, 24: second selector, 25: second storage section, 26: third selector, 27: expected value data input terminal, 28: mask data input terminal, 2
9: Write control unit.

Claims (1)

[Claims] 1. A memory test device that performs a test by accessing a memory under test using addresses sequentially generated from a pattern generator and comparing the output of the memory under test with an expected value pattern in a comparison circuit, comprising: a first storage section; a second storage section, a delay circuit that delays an address from the pattern generator, and a first selector that selects one of the addresses from the pattern generator and the delay circuit to access the first storage section; a second selector that selects an address of one of the pattern generator and the delay circuit to access the second storage section; and a second selector that receives each output of the first storage section and the second storage section, and selects an address of one of the pattern generator and the delay circuit to access the second storage section; A third selector that outputs the output and supplies it to the comparison circuit, or outputs neither of the two inputs, and a mismatch output from the comparison circuit, which is supplied to at least one of the first storage section and the second storage section. A memory test device comprising: a write control section that provides a write pulse.