JPS6132827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with increased breakdown voltage by preventing dielectric breakdown at the surface edge of a PN junction.

When a reverse voltage is applied to the PN junction of a semiconductor device, dielectric breakdown occurs at a predetermined voltage (withstand voltage). The voltage at which this dielectric breakdown occurs is
There is a difference between the inside and the surface where the PN junction terminates, and generally dielectric breakdown occurs at the surface before the dielectric breakdown voltage in the bulk is reached. Therefore, the breakdown voltage of the semiconductor device is the dielectric breakdown voltage of the surface, which is a low breakdown voltage. Furthermore, dielectric breakdown at the surface is unstable and has a large negative effect on semiconductor devices.

For this reason, it is well known that a bevel structure (including a mesa shape) in which the surface shape of the edge of the PN junction surface is processed diagonally improves the dielectric breakdown on the above surface. Compared to, for example, a planar structure semiconductor device formed by terminating a PN junction at the top, it is more labor-intensive to manufacture, and passivation is also difficult, resulting in lower overall reliability.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that is easy to manufacture and has high reliability like a planar structure, and has a breakdown voltage equivalent to that of a mesa structure (bevel structure). With the goal.

That is, the semiconductor device according to the present invention has a first PN formed between a first region of a first conductivity type and a second region of an opposite conductivity type facing one main surface of the semiconductor substrate and provided within the semiconductor substrate. a second PN formed between a third region of an opposite conductivity type facing the main surface and the first region and ending at the main surface;
a junction, the third region is formed with a higher impurity concentration than the second region, and a depletion layer that grows from the first PN junction to the entire thickness within the first region is formed in the second region. The first PN junction is characterized by a structure in which dielectric breakdown occurs at a voltage lower than the dielectric breakdown voltage of the second PN junction by reaching the main surface near the PN junction. a second with an end on the (surface)
Even if the breakdown voltage of the PN junction is exceeded, breakdown will not occur in the second PN junction, and even if the breakdown voltage of the first PN junction is exceeded,
Dielectric breakdown occurs only when the breakdown voltage of the junction is reached. Therefore, the withstand voltage is high, and since dielectric breakdown occurs at the first PN junction in the bulk, it is relatively stable and has little effect on the semiconductor device. Also, since it can have a planar structure,
Surface treatments such as passivation can be easily performed, and reliability and characteristics can be improved.

Next, a first embodiment of the present invention will be described with reference to FIG. A first region 1 of a first conductivity type, for example, P type, facing one main surface (surface) of a semiconductor substrate is epitaxially grown on a second region 2, which is a semiconductor crystal substrate of an opposite conductivity type, for example, N type. A first PN junction 4 is formed at the interface between these first and second regions. Further, a third region 3 is formed around the first region 1 by diffusing impurities of the opposite conductivity type, for example, N type, at a high concentration so as to reach the second region from the surface.
These first and third regions form a second PN junction 5 that terminates at the surface.

Furthermore, on the surface of the P-type first region 1,
An insulating layer 6 such as SiO ₂ is deposited for stabilization, and a P ⁺ type region 7 for leading out the anode electrode is formed by diffusion through the window of this insulating layer 6. Furthermore, an N ⁺ type region 8 for taking out the cathode electrode is formed below the N type second region 2 .

In a semiconductor device (a diode in this example) having such a structure, the thickness x ₁ of the first region 1 and the impurity concentrations N ₁ and N 2 of the first and second regions 1 and ₂ are further set under the following conditions. Select to satisfy. That is, when applying a reverse voltage to the first PN junction 4, the voltage V ₀ at which the entire first region 1 becomes a depletion layer is V ₀ =q/2ε・X ² ₁・N ₁・(1+N ₁ / _N2 )...
Therefore, it is necessary to set this voltage V ₀ lower than the dielectric breakdown voltage BV ₂ of the second PN junction 5 (BV ₂ >V ₀ ). In order to lower the voltage V ₀ , the thickness x ₁ and impurity concentration N ₁ of the first region 1 should be made small, and the impurity concentration N ₂ of the second region 2 should be made relatively large, according to the formula. By the way, the dielectric breakdown voltage BV ₁ at the first PN junction 4 is BV ₁ ≒q/2ε・N ₂・{(ε/qN ₂・Ecrit+xo) ²
− (1 ₊ ^N _{1 /} ^N _{2 )} If it is set too large, BV ₁ will be lowered. For this reason, the preferred range of _N2 is about 1/100 to 10 times _N1 .

On the other hand, the concentration of the high impurity concentration region 8 of the cathode group is set not only for ohmic contact but also for stopping the depletion layer from expanding into the second region 2.
The higher the price, the better. As a result, the first area 1
The depletion layer on the side can be promoted while keeping the breakdown voltage of the first PN junction 4 high.

In this way, the dielectric breakdown voltage BV ₂ of the second PN junction 5
At a lower predetermined voltage V ₀ , a depletion layer is formed over almost the entire area inside the first region 1, so even if a voltage higher than the voltage V ₀ is applied, the rate of increase in the electric field of the second PN junction 5 is It becomes very small. Therefore, even with the conventional withstand voltage BV _2, no dielectric breakdown occurs in the second PN junction 5, and when the voltage reaches an even higher voltage BV ₁ , the electric field of the first PN junction 4 becomes Ecrit, and the first PN junction 4 in this bulk is insulated. Destruction occurs.

The concentration of the high impurity concentration region 7 on the anode side is required to be high not only for ohmic contact but also to prevent a depletion layer from entering therein.

As is clear from the above description, the breakdown voltage of the diode, which is the semiconductor device according to this embodiment, is substantially increased from the conventional surface breakdown voltage BV ₂ to the bulk breakdown voltage BV ₂ . Furthermore, as a semiconductor device, a planar structure in which the PN junction is exposed is possible, which is more advantageous than a mesa structure (bevel structure) in terms of manufacturing and characteristics. Furthermore, since dielectric breakdown occurs within the bulk, it is more stable than surface dielectric breakdown, and has less adverse effects on the element. Furthermore, when the same breakdown voltage as the conventional one is configured, the impurity concentration can be increased by that amount, so the current capacity can be increased.

FIG. 2 shows a second embodiment, in which the electrode 11 connected to the third region 3 is connected to the second PN junction 5 via the insulating layer 6 in the structure of the first embodiment.
and is formed on a part of the first region 1. Since the other configurations are the same as those in the first embodiment, the same reference numerals will be given and the description will be omitted.

In this second embodiment, since the depletion layer also grows from the surface portion of the first region 1 covered with the electrode 11, the voltage at which the entire first region 1 becomes a depletion layer can be kept low, and the semiconductor substrate Conditions such as impurity concentration are relaxed. Furthermore, since the metal electrode 11 is located on the second PN junction 5, the harmful effects of external ions are prevented, and the leakage current flowing across the second conductive junction 5 is reduced.

FIG. 3 shows a third embodiment in which the present invention is applied to an epitaxial base type planar transistor. An example of a method for manufacturing this transistor is shown in FIGS. 4A to 4E.

That is, in FIG. 4A, the first region P
A first PN junction 4 is formed between the type epitaxial base layer 1 and the N type silicon crystal substrate 2 which is a second region, and the surface of the P type epitaxial layer 1 is insulated with SiO ₂ by thermal oxidation. The layer 6 has a high concentration N-type layer 8 on the lower surface of the N-type substrate 2 for extracting the collector electrode.
are formed respectively.

Next, as shown in FIG. 4B, an N ⁺ diffusion region 3 serving as a third region is formed around the P-type epitaxial layer 1 so as to reach the N-type substrate 2, and a gap between these first and third regions is formed. A second PN junction 5 is obtained. Of course, the second PN junction 5 is connected to the first PN junction 4 at its lower end.

Next, in FIG. 4C, P type and N type impurities are sequentially diffused from the same window for emitter diffusion to form a P type region ₇₁ and a heavily doped N type region 9 as an emitter region. The P-type region ₇₁ is for preventing emitter punch-through, and has a higher impurity concentration than the P-type epitaxial layer 1. The base region includes a first region 1 and a P-type region 7 ₁
It is composed of

In FIG. 4D, a high-purity P type impurity from the window portion of the base is diffused to form a P ⁺ diffusion region ₇₂ for extracting the base electrode. At this time, the distance between the P-type regions 7 ₁ and 7 ₂ is preferably set to a small value so that a part of the P-type epitaxial layer 1 between them remains without being depleted.

Next, in FIG. 4E, the P ⁺ region 7 ₂ ,
By opening a window for electrode extraction on the N ⁺ region 9, and further depositing a metal layer such as A and photo-etching it, an epitaxial base type transistor having a base and an emitter electrode as shown in FIG. 3 is formed. is obtained.

In this third embodiment, the first and second PN
When the reverse voltage to the junctions 4 and 5 is increased, the depletion layer grows from these PN junctions at a faster rate toward the lower concentration region. and,
At a predetermined voltage V ₀ that is lower than the dielectric breakdown voltage of the surface end a of the second PN junction 5, the entire first region 1 is filled with a depletion layer. However, regions 3 and 7 with high impurity concentration
The inside of regions 7 ₁ and 7 ₂ and the surface portion between regions 7 ₁ and 7 ₂ remain without being depleted. Furthermore, even if a reverse voltage higher than the voltage V ₀ is applied, the second PN junction 5
The electric field at the surface end a remains almost unchanged. On the other hand, the electric field of the first PN junction 4 increases as the reverse voltage increases, so that the predetermined dielectric breakdown voltage BV ₁
When this reaches, dielectric breakdown occurs near portion b of the first PN junction 4.

In this way, the conditions for almost the entire first region 1 to become a depletion layer at a voltage lower than the dielectric breakdown voltage of the second PN junction 5 are the same as in the first embodiment described above.

Therefore, the breakdown voltage of the transistor is increased to the breakdown voltage of the first PN junction inside the element. This corresponds to the withstand voltage of a mesa transistor that prevents dielectric breakdown at the surface. Moreover, since the structure is planar, it is easy to manufacture and has high reliability. Furthermore, compared to conventional planar transistors with the same breakdown voltage, the impurity concentration of the N-type substrate 2 can be increased, and the current capacity can be increased. Furthermore, the internal base resistance due to the P-type diffusion region ₇₁ under the emitter region 9 is small, and the P-type epitaxial layer 1
Since the external base resistance is large and can be controlled individually, it is possible to make the current density more uniform even during large current operation, for example, and to expand the area of safe operation (ASO).

Next, FIG. 5 shows a fourth embodiment, and in the explanation of the third embodiment, a highly doped P-type diffusion base layer ₇₃ is formed in the P-type epitaxial base layer 1 of FIG. 4B. Furthermore, a high concentration of N is added to this P ⁺ base layer ₇₃ .
A type of diffused emitter layer is formed.

The operation of this fourth embodiment is also substantially the same as that of the third embodiment, and it is obvious that it has effects such as high breakdown voltage, high reliability, and improved ASO. Furthermore, since the P-type regions 7 ₁ and 7 ₂ of the embodiment shown in FIG. 3 are connected, the absolute value of the base resistance becomes smaller, and, for example, the switching speed is improved.

These third and fourth embodiments can also have a protruding electrode structure similar to the second embodiment described above, and as an example, in the third embodiment, the protruding electrode structure is A fifth embodiment employing the above is shown in FIG. 6 as a fifth embodiment. Since the structure, operation, and effect are the same as those of the second and third embodiments, the reference numerals in FIG. 6 are the same as those of the second and third embodiments, and a description thereof will be omitted.

Note that the present invention is not limited to the first to fifth embodiments described above, and for example, P type and N type may be used interchangeably. In addition, as a semiconductor device,
Not limited to diodes and transistors, but also FETs
Of course, it can be applied to various things such as (field effect transistor) and bipolar IC.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing a first embodiment of the present invention, Fig. 2 is a sectional view showing a second embodiment, Fig. 3 is a sectional view showing a third embodiment, and Fig. 4A. ~E is a sectional view along the manufacturing process of the third embodiment,
The figure is a sectional view showing the fourth embodiment, and FIG. 6 is a sectional view showing the fifth embodiment. 1...First area, 2...Second area, 3...Third area
Region, 4...first PN junction, 5...second PN junction, 6...insulating layer.

Claims (1)

[Claims] 1. A first semiconductor substrate of a first conductivity type facing one principal surface of a semiconductor substrate.
a first PN junction formed between the region and a second region of opposite conductivity type and provided within the semiconductor substrate; and a third region of opposite conductivity type formed facing the main surface.
a second PN junction formed between the region and the first region and terminating at the main surface; the third region is formed with a higher impurity concentration than the second region; A depletion layer that grows from the junction to the entire thickness inside the first region forms the second PN.
A semiconductor device characterized in that dielectric breakdown occurs in the first PN junction at a voltage lower than the dielectric breakdown voltage of the second PN junction by reaching the main surface near the junction.