JPS6132990B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printing pattern conversion device suitable for printing devices that require various output forms of character patterns.

In general, information equipment such as office computers,
For example, a word processor or the like is equipped with a display device such as a raster scan type CRT display device, and a printing device such as a high speed serial wire dot printer. However, when displaying or printing certain characters or symbols,
The corresponding character pattern in the dot matrix structure. Output to CRT display device or printing device. The above-mentioned character patterns are stored in a character pattern memory (so-called character generator), which is usually composed of RAM (random access memory) or the like.

By the way, the output formats of character patterns for display and printing are generally different.
The details will be explained using a kanji pattern with a 24 x 24 dot matrix as an example. That is, since kanji patterns are generally complex, they are divided into several parts and processed. For example, the character "bun" is divided into 72 division patterns 0a to 71a as shown in FIG. In this case, one division pattern consists of 8 bits. Then, 72 division patterns 0a to 7
1a are stored at consecutive address locations in the character pattern memory, as shown in FIG. The 72 division patterns 0a to 71a stored in this way are
The divided patterns 1a, . . . , the divided patterns 71a are read out from the character pattern memory in this order. Therefore, as is clear from FIG. 1, the division patterns 0a to 71a are used, for example, when displaying characters "sentence" on a CRT display device.

On the other hand, in order to print characters "sentence" horizontally using, for example, a serial wire dot printer in which printing pins are arranged vertically, characters are divided into 72 division patterns 0b to 71b as shown in Figure 3. It is necessary to use a pattern. Similarly,
In order to print the characters "sentence" vertically, it is necessary to use a character pattern divided into 72 division patterns 0c to 71c as shown in FIG.

Therefore, in order to perform display, horizontal printing, and even vertical printing, three types of character patterns are stored in the character pattern memory for each character (character patterns for CRT display, horizontal printing, and vertical printing). must be stored. For this reason, the memory capacity of the character pattern memory becomes extremely large, especially in information devices that handle character patterns such as Kanji patterns that require a large pattern memory capacity per character. In other words, the cost of the character pattern memory becomes extremely high.

The present invention has been made in view of the above circumstances, and its purpose is to convert the arrangement of character patterns output from a character pattern memory in a specific output format, and to output a character pattern for printing that is particularly suitable for vertical printing. An object of the present invention is to provide a printing pattern conversion device that enables printing patterns to be converted.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a block diagram showing the configuration of a print pattern conversion device 11 according to an embodiment of the present invention. In the figure, reference numeral 12 is a character pattern memory. The character pattern memory 12 stores various character patterns such as Chinese characters, alphanumeric characters, symbols, etc. in the form of divided character patterns shown in FIG. 1, for example, as shown in FIG. 2. That is, in the embodiment of the present invention, character patterns are stored in the character pattern memory 12 so as to be suitable for a display device such as a CRT display device. In other words, the output form of the character pattern memory 12 is
Suitable for outputting character patterns to CRT display devices.

Reference numeral 13 denotes a buffer memory that holds character patterns read from the character pattern memory 12 in a predetermined memory area, and also holds print data to be output to a printing device (not shown). code 1
4 accesses the buffer memory 13. This is a memory access control unit. This memory access control section 14 includes a buffer memory control circuit 15.
Writing to and reading from the buffer memory 13 is performed according to the memory address sequence specified by . The buffer memory control circuit 15 requests character pattern transfer to the character pattern memory 12;
Mode set flip-flops 23, 2 to be described later
4, 25, and the access control section 14
It is used to control, etc.

Reference numeral 16 denotes a demultiplexer that switches and outputs the readout output of the buffer memory 13 to a printing device (not shown) or a register 17. This demultiplexer 16 sends the readout output of the buffer memory 13 to the register 17 when a mode set flip-flop 23, which will be described later, is in the set state. On the other hand, when the mode set flip-flop 23 is in the reset state, the demultiplexer 16 sends the read output to the printing device.

The register 17 is, for example, an 8-bit shift register for pattern conversion capable of parallel input/output and serial output (shift up, shift down).
This register 17 is the buffer memory control circuit 15.
When vertical printing is performed, a downshift operation is performed, and when horizontal printing is performed, a shift up operation is performed. Reference numeral 18 is a 1-bit register that holds 1-bit overflow data (hereinafter referred to as shift-up data) accompanying the shift-up operation of the register 17. code 1
A selector 9 selectively outputs either overflow data (hereinafter referred to as shift-down data) or data held in the register 18 for the shift-down operation of the register 17. This selector 19 selectively sends out shift down data when a mode set flip-flop 24, which will be described later, is in the set state. On the other hand, when the mode set flip-flop 24 is in the reset state,
The selector 19 selectively outputs the data held in the register 18.

Reference numeral 20 is a register for pattern conversion.
This register 20 is, for example, an 8-bit shift register capable of serial input and parallel output. The register 20 inputs the output of the selector 19 in series starting from the least significant bit position, and outputs the output in parallel when 8 bits are input. A selector 21 selectively outputs either the parallel output data of the register 17 or the parallel output data of the register 20. This selector 21 selectively outputs the parallel output data of the register 20 when a mode set flip-flop 25, which will be described later, is in the set state. On the other hand, when the mode set flip-flop 25 is in the reset state, the selector 21
selectively outputs the parallel output data of the register 17.

A selector 22 selectively outputs either the read output of the character pattern memory 12 or the output of the selector 21 to the buffer memory 13. The selector 22 selects the output of the selector 21 when the mode set flip-flop 23 is in the set state, and selects the output of the selector 21 when the mode set flip-flop 23 is in the reset state.
Select the output of the character pattern memory 12.

The mode set flip-flop 23 is a flip-flop circuit that specifies a pattern conversion mode and is controlled by the buffer memory control circuit 15. This mode set flip-flop 23 is set during pattern conversion.
It is reset during other periods. A mode set flip-flop 24 is a flip-flop circuit that specifies a pattern conversion method and is controlled by the buffer memory control circuit 15. This mode set flip-flop 2
4 is set when vertical printing pattern conversion is specified,
It is reset when horizontal printing pattern conversion is specified.
Further, a mode set flip-flop 25 is a flip-flop circuit that is used to specify a register in which data to be written to the buffer memory 13 is held, and is controlled by the buffer memory control circuit 15. The mode set flip-flop 25 is set when writing of vertical or horizontal print data after pattern conversion is specified, and is reset after writing a predetermined number of bits, for example 8 bits (one byte).

Next, the operation of the print pattern conversion device 11 configured as described above will be explained. First, the case of realizing the output order of character patterns shown in FIG. 3, that is, the case of outputting a horizontal print pattern will be described. For example, buffer memory control circuit 1
It is assumed that a read command is issued from 5 to the character pattern memory 12. As a result, the corresponding character pattern is read byte by byte in the output order shown in FIG. At this time, the mode set flip-flop 23 has been reset, so that the selector 22 selectively sends the read output of the character pattern memory 12 to the buffer memory 13.

On the other hand, the buffer memory control circuit 15 specifies a memory address sequence to the memory access control section 14. Thereby, the memory access control unit 14 sends a write pulse and address data to the buffer memory 13 in synchronization with the readout output of the character pattern memory 12. However,
The character pattern read from the character pattern memory 12 is written into a predetermined memory area of the buffer memory 13 as shown in FIG.

Next, buffer memory control circuit 15 sets mode set flip-flop 23 to designate a pattern conversion mode. As a result, the read output of the buffer memory 13 is sent to the register 17 by the demultiplexer 16. On the other hand, the memory access control section 14 sends out a memory access sequence corresponding to horizontal printing pattern conversion to the buffer memory 13 in response to a command from the buffer memory control circuit 15. As a result, the buffer memory 13 first outputs 1-byte leading data, that is, the divided character pattern 0a shown in FIGS. 1 and 2. This divided character pattern 0a is input in parallel to the register 17 via the demultiplexer 16. Thereafter, the register 17 shifts up by 1 bit, so that the shift-up data, that is, the most significant bit of the 1-byte divided character pattern 0a, is transferred to the register 18.
is maintained.

For horizontal print pattern conversion, mode set flip-flop 24 is in a reset state. The selector 19 selectively outputs the data held in the register 18, that is, the most significant bit of the divided character pattern 0a, to the register 20. The most significant bit of the divided character pattern 0a is serially input to the register 20 and held at the least significant bit position. After that, the above-mentioned operation is performed on divided character patterns 3a, 6a, 9a, 12a, 15a,
This is repeated in sequence for 18a and 21a. Each time the most significant bit of each divided character pattern is sequentially input to the register 20, the register 20 performs a shift-up operation. Therefore,
When the most significant bit of the divided character pattern 21A is input to the register 20, the most significant bit of the divided character pattern 0a is placed in the most significant bit position of the register 20, and the most significant bit of the divided character pattern 21a is placed in the least significant bit position of the register 20. The upper bits are retained. That is, the 1-byte data held in the register 20 is the divided character pattern 0b shown in FIG. 3, and pattern conversion for horizontal printing is performed. 1 in register 20
When a byte of data is held, buffer memory control circuit 15 sets mode set flip-flop 25. As a result, the selector 21 selectively outputs the data held in the register 20 to the selector 22. The selector 22 sends the output data of the selector 21 to the buffer memory 13 according to the set state of the mode set flip-flop 23. The output data of the selector 21, that is, the divided character pattern 0b, is stored in the buffer memory 1.
It is written to the first address in the predetermined memory area of No. 3.

The mode set flip-flop 25 transfers the data held in the register 20 to the buffer memory 1.
It is reset except when writing to 3. That is, the selector 21 selectively outputs the data held in the register 17 during a period other than the writing time. In the embodiment of the present invention, the data held in the register 17 is returned to the original address in the buffer memory 13 via the selectors 21 and 22 and written therein, after being shifted up by one bit as described above. Therefore, each divided character pattern returned to the original address of the buffer memory 13 in this way is the divided character pattern 0a,
3a, 6a, 9a, 12a, 15a, 18a, 2
It is not the same as 1a. That is, the most significant bit of each divided character pattern returned to the original address in the buffer memory 13 is the bit one bit lower than the most significant bit in the original divided character pattern. This is because the divided character pattern 3b shown in FIG. 3 is obtained by the operation described above.

When the divided character pattern 0b is written into the buffer memory 13, the divided character patterns 24a, 27a, 30a, 33 are subsequently written from the buffer memory 13.
a, 36a, 39a, 42a, and 45a are read out sequentially. Then, the same process as described above is performed, and the divided character pattern 1b is written to the next address in the buffer memory 13 after the address where the divided character pattern 0b is written. Similarly, divided character patterns 48a, 51
a, 54a, 57a, 60a, 63a, 66a,
69a, a divided character pattern 2b is obtained.

Next, as mentioned above, the divided character patterns 0a, 3 returned to the original address of the buffer memory 13
a, 6a, 9a, 12a, 15a, 18a, 21
a are read out sequentially. Then, a divided character pattern 3b is obtained. Thereafter, the above-mentioned operation is repeated, and the divided character pattern 0 shown in FIG.
b, 1b, ..., 71b are obtained. The divided character patterns 0b to 71b are sequentially stored in a predetermined memory area of the buffer memory 13. That is,
The character pattern shown in Figure 1 is converted to a character pattern for horizontal printing as shown in Figure 3,
This means that the buffer memory 13 is stored in an output format suitable for horizontal printing. Therefore, there is no need to store character patterns for horizontal printing in the character pattern memory 12, and the memory capacity of the character pattern memory 12 can be reduced.

Next, a case will be described in which the output order of character patterns shown in FIG. 4 is realized, that is, a case in which vertically written print data is output. In this case, the mode set flip-flop 24 is set and the selectors 21, 2
2. The demultiplexer 16 operates in the same manner as described above.

It is now assumed that character patterns are stored in a predetermined memory area of the buffer memory 13 as shown in FIG. 2 by the same procedure as described above. Therefore, the buffer memory control circuit 1
5. Under the control of the memory access control section 14, the divided character pattern 2a is read out from the buffer memory 13. This divided character pattern 2a is input in parallel to the register 17 via the demultiplexer 16. Thereafter, the register 17 shifts down one bit at a time, and as a result, shift down data is serially output from the register 17.

On the other hand, in the case of vertical print pattern conversion, the mode set flip-flop 24 is in the set state. Therefore, the selector 19 transfers the shift down data output from the register 17 to the register 2.
Selectively output to 0. Then, the shift down data is serially input to the register 20 starting from the least significant bit position. Therefore, by continuing the shift operation eight times in the register 17, 8 bits (1 byte) of data is held in the register 20. The data held in this register 20 has a bit arrangement that is opposite to that of the divided character pattern 2a input in parallel to the register 17. That is, the 1-byte data held in the register 20 is the divided character pattern 0c shown in FIG. 4, and pattern conversion for vertical printing is performed. The data held in the register 20, that is, the divided character pattern 0c, is transferred to the buffer memory 13 through the selectors 21 and 22 in order by the same procedure as described above.
is written to the first address in a predetermined memory area.

After the divided character pattern 0c is written into the buffer memory 13, the divided character pattern 1a is subsequently read out from the buffer memory 13. This divided character pattern 1a is processed in the same manner as the above-mentioned divided character pattern 2a. That is, the bits of the divided character pattern 1a are reversed by the registers 17 and 19. The divided character pattern 1a is the divided character pattern 1 shown in FIG.
As c, the upper divided character pattern 0c in the buffer memory 13 is written to the next address of the address written therein. Similarly, divided character pattern 0a is written as divided character pattern 2c at the address next to the address where divided character pattern 1c is written. Hereinafter, the above-mentioned operation will be applied to divided character patterns 5a, 4a, 3a, 8a, 7a,
6a, . . . , 71a, 70a, 69a are sequentially performed. Then, the divided character pattern 5a becomes the divided character pattern 3c, the divided character pattern 4a becomes the divided character pattern 4c, and the divided character pattern 3a becomes the divided character pattern 3c.
is the divided character pattern 5c, the divided character pattern 71a is the divided character pattern 69c, and the divided character pattern 70a is the divided character pattern 70c.
Further, each divided character pattern 69a is converted into a divided character pattern 71c. Therefore, the above-mentioned divided character patterns 3c, 4c, 5
c, . . . , 71c are sequentially written into a predetermined memory area following the divided character pattern 2c in the buffer memory 13. That is, the character pattern shown in FIG. 1 is converted into a character pattern for vertical printing as shown in FIG. 4, and is stored in the buffer memory 13 in an output format suitable for vertical printing. become. Therefore, there is no need to store character patterns for vertical printing in the character pattern memory 12, and the memory capacity of the character pattern memory 12 can be reduced.

Next, other embodiments of the present invention will be described.
FIG. 6 shows another embodiment of the present invention, and is a block diagram showing the configuration of a print pattern conversion device 31. The print pattern conversion device 31 includes a character pattern memory 32 and a random access memory (hereinafter referred to as
33 (hereinafter referred to as RAM), a microprogram sequencer 34, an arithmetic processing unit (hereinafter referred to as CPU) 35, and a printer driver 36. Here, the character pattern memory 32 and RAM 33 are respectively the character pattern memory 12 and buffer memory 1 explained in the above embodiment.
This corresponds to 3. Further, the microprogram sequencer 34 and the CPU 35 include the buffer memory control circuit 15, the memory access control section 14, the registers 17 and 20, and the selector 1.
9, 21, 22, etc.

Micro program sequencer 34 is CPU 3
5, it instructs procedures etc. for controlling various hardware, and is composed of a read-only memory (hereinafter referred to as ROM) 37, a program counter 38, a register 39, and a microprogram controller 40. There is. ROM37
A microprogram for realizing the control procedure as shown in the above embodiment is stored in the microprogram.
The program counter 38 specifies the next microaddress to be executed.
The microinstruction is read from the corresponding address of 37. This microinstruction is held in register 39. A predetermined field of the microinstruction held in this register 39 is decoded by a microinstruction decoder (not shown). This decoding result is used as a control signal for various hardware such as the CPU 35, program counter 38,
It is given to the microprogram controller 40 and the like. This micro program controller 4
0 is the ROM3 according to the calculation processing result of the CPU35.
In addition to performing access control corresponding to 7.
It controls the hardware within the CPU 35.

The CPU 35 is controlled by a control signal based on the above-mentioned microinstructions and a microprogram controller 40, and performs the corresponding arithmetic processing, and the CPU 35 is provided with registers 41, 42, etc. for holding the arithmetic results. . The registers 41 and 42 correspond to the registers 17 and 20 in the embodiment described above, respectively. Further, the printer driver 36 sends the printing pattern data read from the RAM 33 in units of 3 bytes (24 bits) to a printing device (not shown) at a predetermined timing.

In this embodiment, the RAM 33 includes a first storage area (for example, addresses 0 to 71) in which character patterns for one character are written, which are sequentially read out in units of divided character patterns by the character pattern memory 32; A second storage area (for example, addresses 80 to 151) is provided in which print pattern data after pattern conversion is written in units of divided character patterns.

Hereinafter, the operation of the print pattern conversion device 31 configured as shown in FIG. 6 will be explained with reference to the flowcharts shown in FIGS. 7 to 10.
The contents of this flowchart basically match the procedure of the pattern conversion operation in the embodiment described above.

First, upon pattern conversion, the CPU 35 accesses the character pattern memory 32 and converts a predetermined character pattern into divided character patterns 0a, 1a, 2a,
..., 71a are read and output in this order. Furthermore, the CPU
35 is the above divided character pattern 0a to 71a.
The data is sequentially stored in addresses 0 to 71 of the RAM 33 (step S1). Next, a check is made to see if the pattern conversion is for horizontal printing (step S2), and if the pattern conversion is for horizontal printing, the process goes to step S3, and if the pattern conversion is for vertical printing, the process goes to step S4. move on. For example, assume that pattern conversion for horizontal printing is specified and the process advances to step S3.

In step S3, the RAM address N of the first storage area in the RAM 33 is set to "0" (N=0).
Similarly, the RAM address P of the second storage area is set to "80" (P=80). Further step S3
In this case, each conversion step Q, R, S, T is set to "0" (Q=0, R=0, S=0,
T=0). Here, the conversion step Q is to check whether the converted pattern data has been collected for one divided character pattern (one byte), and when Q = 8, the converted one divided character pattern is obtained. That means that. Also, the conversion step R
is for checking whether the conversion of one slice, that is, the three-part character pattern has been completed, and it has been completed when R=3. In addition, in the conversion step S, the conversion for one slice described above is 8
This is to check whether it has been repeated twice or not, and it ends when S=8. Furthermore, the conversion step T is for checking whether the above-mentioned conversion for 8 slices has been repeated three times, that is, whether the pattern conversion for one character has been completed. become.

Next, the contents of the RAM address N of the RAM 33 (in this case, N=0, so the contents of address 0, that is, the divided character pattern 0a) are read by the CPU 35 and then held in the register 41 (step S5). . Then, the register 41 shifts up the held data by one bit (step S6). Next, the process advances to step S6, where the register 41
It is checked whether carry data ("1") is output by the shift operation. If the carry data ("1") is output, that is, if the overflow data indicates the logical value "1", the process advances to step S8. On the other hand, carry data (“1”)
If the overflow data is not output, that is, if the overflow data indicates the logical value "0", the process advances to step S9. In step S8, data indicating a logical value "1" is set in the least significant bit position of the register 42, and in step S9, data indicating a logical value "0" is set in the least significant bit position of the register 42. In either case, step S10
Proceed to.

In step S10, the contents of the register 41, that is, the data held after the 1-bit shift-up operation, is specified by the RAM address N (in this case, N
=0) The data is returned to the address location of the RAM 33, that is, the original address location, and stored. Next, the process advances to step S11, and the value of the conversion step Q is "+".
1" (Q=Q+1), and as a result, the value of the conversion step Q becomes "1". Then, the conversion step Q
It is checked whether the value of is "8" or not (step S12), and if it is not "8", the process proceeds to step S1.
If the value is "8", the process advances to step S14. Now, the value of conversion step Q is "1",
Therefore, the process of step S13 is performed.
In step S13, the data held in the register 42 is shifted up by one bit. As a result, the least significant bit position of register 12 becomes vacant.

Next, in step S15, the value of RAM address N is incremented by "+3" (N=N+3), and then the process of step S5 is performed again. Note that, as described in detail in the above embodiment, the processing in step S15 is performed, for example, for divided character patterns 0a, 3a, 6.
For sequentially reading a, 9a, ... from RAM33
This is to set the RAM address N. Then, the above-mentioned steps S5, S6, S7, S8,
S9, S10, S11, S12, S13, S15
It is assumed that the process is repeated and the value of the conversion step Q becomes "8". At this time, each divided character pattern 0a, 3a, 6 is stored in the register 42.
The most significant bits of a, 9a, 12a, 15a, 18a, and 21a, that is, the divided character pattern 0b should be held.

If the value of the conversion step Q is "8", the process of step S14 is performed as described above.
In step S14, the content of the register 42, that is, the divided character pattern after pattern conversion (in this case, divided character pattern 0b) is stored in the RAM 33 specified by the RAM address P (in this case, P=80).
is stored at the address location. Next step S1
6, the values of RAM address P and conversion step R are each increased by 1 (P=P+1, R
=R+1), while the value of the conversion step Q is again set to "0" (Q=0). Process here [P=
P+1] is the RAM that should store the next divided character pattern after conversion (in this case, divided character pattern 1b)
This is to specify 33 addresses. Furthermore, processing [Q=0] indicates the first step of the next pattern conversion, and processing [R=R+1] (R=1 in this case) specifies the number of converted divided character patterns in one slice. It is something to do.

Next, in step S17, it is checked whether the value of conversion step R is "3".
If it is not "3", go to step S15 again;
If it is "3", the process advances to step S18. The value of the conversion step R is now "1", so the process of step S15 is performed. It is assumed that the processing of each step described above is repeated and the value of the conversion step R reaches "3".
At this time, addresses 80 to 82 of the RAM 33 contain divided character patterns 0b, 1b, 2b after conversion, respectively.
should be stored. In other words, pattern conversion for one slice should have been completed.

If the value of the conversion step R is "3", the process of step S18 is performed as described above.
In step S18, the value of RAM address N is set to "-69" (N=N-69), and the value of conversion step R is set to "0" again (R=0). Here, processing [N=N-69] is divided character pattern 0a, 1
Either a or 2a is specified, and in this case, divided character pattern 0a is specified again. Further, in step S18, the value of the conversion step S is incremented by ``1'' (S=S+1), and in this case, the value of the conversion step S becomes ``1''.

Next, in step S19, it is checked whether the value of the conversion step S is "8". Then, if it is not "8", go to step S5 again.
If it is "8", the process advances to step S20. Now, the value of the conversion step S is "1", so the process of step S5 is performed. In this step S5, the divided character pattern 0a read from the RAM 33 is changed from the original divided character pattern 0a.
It is clear that it is not the same as a. This has been explained in detail in the above embodiments, so the explanation will be omitted. It is assumed that the processing of each step described above is repeated and the value of the conversion step S becomes "8". At this time, the divided character patterns 0b to 23b after conversion should be stored at addresses 80 to 103 of the RAM 33, respectively.
In other words, pattern conversion for eight slices should have been completed.

If the value of the conversion step S is "8", the process of step S20 is performed as described above.
In step S20, the value of RAM address N is incremented by "+1" (N=N+1), and the value of conversion step S is again set to "0" (S=0). Here, processing [N=N+1] specifies either divided character pattern 1a or 2a to be converted next every time pattern conversion for 8 slices is completed. Pattern 1a is specified. Further, in step S20, the value of the conversion step T is incremented by ``1'' (T=T+1), and in this case, the value of the conversion step T becomes ``1''.

Next, in step 21, it is checked whether the value of the conversion step T is "3". Then, if it is not "3", go to step S5 again.
If it is "3", the process advances to step S22. Now, the value of the conversion step T is "1", so the process of step S5 is performed. and,
The processing of each step described above is repeated for divided character patterns 1a, 4a, 7a, ..., 70a, and further for divided character patterns 2a, 5a, 8.
Assume that the conversion is repeated for a, . . . , 71a, and the value of the conversion step T becomes "3". At this time, the divided character patterns 0b to 71b after conversion should be stored at addresses 80 to 151 of the RAM 33, respectively. In other words, pattern conversion for one character should have been completed.

When the value of the conversion step T is "3", that is, when the pattern conversion for one character is completed, the process of step S22 is performed as described above. In step 22, addresses 80 to 151 of RAM 33 are
Divided character patterns 0b to 7 stored in address
1b is sent to the printing device via the printer driver 36 as pattern data for horizontal printing.

Next, a case will be described in which pattern conversion for vertical printing is performed. At this time, as described above, the process advances from step S2 to step S4. Step S
4, the RAM address N is "2" (N=2),
RAM address P is set to "80" (P=80). Furthermore, in step S4, each conversion step Q,
R and S are each set to “0” (Q=0,
R=0, S=0). Here, conversion steps Q, R
has the same meaning as in the case of pattern conversion for horizontal printing. On the other hand, the conversion step S, unlike the case of pattern conversion for horizontal printing, checks whether conversion for one slice is performed 24 times. That is, the conversion step S checks whether the pattern conversion for one character has been completed, and is completed when S=24.
Therefore, in the case of pattern conversion for vertical printing in the embodiment of the present invention, introduction of the conversion step T is unnecessary.

Next, the contents of RAM address N of RAM 33 (in this case, N=2, so the contents of address 2, ie, divided character pattern 2a) are read out by CPU 35 and then held in register 41 (step S31). Then, the register 41 shifts down the held data by 1 bit (step S
32). Next, the process advances to step S33, and the register 4
It is checked whether borrow data ("1") is output by the 1 shift operation. When borrow data ("1") is output, that is, when overflow data indicates a logical value "1", the process advances to step S34. On the other hand, if the borrow data ("1") is not output, that is, if the overflow data indicates the logical value "0", the process advances to step S35. The processing contents of steps S34 and 35 are the same as the processing contents of steps S8 and S9 described above, so a description thereof will be omitted. Then, steps S34 and S3
5. In either case, proceed to step S36.

In step S36, the value of the conversion step Q is incremented by "+1" (Q=Q+1), and in this case, the value of the conversion step Q becomes "1". Then, it is checked whether the value of the conversion step Q is "8" (step S37), and if it is not "8", the value of the conversion step Q is checked.
If the value is "8", the process advances to step S39. The value of the conversion step Q is now "1", so the process of step S38 is performed. In step S38, the data held in the register 42 is shifted up by one bit, so that the least significant bit position of the register 42 becomes vacant. Then, each of the above steps S32 and S3
3, S34, S35, S36, S37, and S38 are repeated, and the value of the conversion step Q becomes "8". At this time, register 4
2 should hold a divided character pattern 0c with a reverse bit arrangement to that of the divided character pattern 0a.

If the value of the conversion step Q is "8", the process of step S39 is performed as described above.
In step S39, the contents of the register 42, that is, the divided character pattern after pattern conversion (divided character pattern 0c in this case) is stored in the address position of the RAM 33 designated by the RAM address P (P=80 in this case). Next, step S4
0, and as in step S16 described above, the RAM
The values of address P and conversion step R are each increased by 1 (P=P+1, R=R+1), while the value of conversion step Q is set to 0 again (Q
=0).

Next, in step S41, as in step S17 described above, it is checked whether the value of the conversion step R is "3" or not. If it is not "3", the process advances to step S42; The process advances to step S43. The value of conversion step R is now "1"
Therefore, the process of step S42 is performed. In step S42, the value of RAM address N is set to "-1" (N=N-1). Here, the process of step S42 is performed by setting a RAM address N for sequentially reading out divided character patterns 1a and 0a from the RAM 33 following divided character pattern 2a, for example, as described in detail in the above embodiment. be. This includes divided character patterns 4a, 3a, . . . following divided character pattern 5a, and divided character patterns 70a, 6 following divided character pattern 71a.
The same applies to 9a.

When the process of step S42 is completed, the process returns to step S31. It is assumed that the processing of each step described above is repeated and the value of the conversion step R becomes "3". At this time, RAM33 is 80
Character patterns 0c, 1c, and 2c after conversion should be stored at addresses 82 to 82, respectively. In other words, pattern conversion for one slice should have been completed.

If the value of the conversion step R is "3", the process of step S43 is performed as described above.
At step 43, the value of the conversion step R is again set to "0" (R=0), and the value of the conversion step S is increased by "+1" (S=S+1).

Next, in step S44, it is checked whether the value of the conversion step S is "24" or not. If it is not "24", the process advances to step S45, and if it is "24", the process advances to step S22. The value of the conversion step S is now "1", so the value of the conversion step S4 is
Processing No. 5 is performed. In step S45,
The value of RAM address N is increased by “+5” (N=N
+5). This process is performed by dividing character patterns 5a and 8.
It specifies either a, ..., 71a,
In this case, where the value of RAM address N is "0", N=5, and divided character pattern 5a is specified.

Next, the process advances to step S31, and from then on, the processing of each step described above is repeated for the divided character patterns 5a, 4a,
3a, divided character patterns 8a, 7a, 6a,...
This is repeated for divided character patterns 71a, 70a, and 69a. Then, the conversion step S
Assume that the value of is now "24". At this time,
The divided character patterns 0c to 71c after conversion should be stored at addresses 80 to 151 of the RAM 33, respectively. In other words, pattern conversion for one character should have been completed.

When the value of the conversion step S is "24", that is, when the pattern conversion for one character is completed, the process of step S22 is performed as described above. In step S22, address 80 of RAM 33
Divided character pattern 0c stored at address 151
71c are sent to the printing device via the printer driver 36 as pattern data for vertical printing.

In the above embodiment, a case was explained in which a kanji pattern with a 24 x 24 dot matrix structure was converted, but for example, when converting a character pattern with a 32 x 32 dot matrix structure, and further a character pattern with a 16 x 32 dot matrix structure. can also be easily applied. Furthermore, although the case has been described in which reading and writing are performed in units of divided character patterns each having a 1-byte (8-bit) configuration, the bit configuration of the divided character patterns is not limited to this. That is, the printing pattern conversion method of the present invention can be easily implemented for a character pattern consisting of a divided character pattern of N bits, in which at least the vertical dot matrix structure is an arbitrary integer multiple of the above-mentioned N. be.

Furthermore, in the above embodiment, the character pattern to be converted is
Although the case of a character pattern for CRT display has been described, the present invention is not limited to this, and can be applied to other character patterns by changing the reading order, direction of shift operation, etc.

As described in detail above, according to the present invention, the arrangement of character patterns output from the character pattern memory is converted in a specific output format, and printing that makes it possible to output a character pattern for printing particularly suitable for vertical printing. A pattern conversion device can be provided.

[Brief explanation of the drawing]

Figures 1 to 4 show examples of character pattern configurations. Figure 1 is a diagram showing the configuration of character patterns for CRT display, Figure 2 is a diagram showing the memory storage state of character patterns for CRT display, and Figure 3 is a diagram showing the structure of character patterns for CRT display. 4 is a configuration diagram of a character pattern for horizontal writing printing, FIG. 4 is a configuration diagram of a character pattern for vertical writing printing, and FIG. 5 relates to an embodiment of the present invention. 6 to 10 are block diagrams showing the configuration of a printing pattern conversion device, and FIGS. 6 to 10 show other embodiments of the present invention. FIG. 6 is a block diagram showing the configuration of the printing pattern conversion device, and FIGS. 7 to 10 FIG. 10 is a flowchart for explaining the operation. 11, 31...Print pattern conversion device, 12, 3
2...Character pattern memory, 13...Buffer memory, 14...Memory access control section, 15...Buffer memory control circuit, 17, 18, 20, 41, 4
2...Register, 19, 21, 22...Selector, 2
3-25...Mode set flip-flop, 33
... Random access memory (RAM), 34... Micro program sequencer, 35... Arithmetic processing unit (CPU), 37... Read only memory (ROM), 4
0...Microprogram controller.

Claims (1)

[Claims] 1. A first storage area in which one character's worth of display character pattern data having a dot matrix structure of n rows by m columns is read out in N-bit divided character pattern units from the character pattern memory, and a second storage area. in a first conversion mode, an address sequence in which the read address for the first storage area of the memory is increased n-1 times by m/N is repeated m times, and The read start address is advanced by one for each sequence, and in the second conversion mode,
The address sequence in which the read address for the first storage area of the memory is decreased by 1 (m/N)-1 times is repeated n times, and the read start address is advanced by m/N for each address sequence, and the read address for the first storage area of the memory is decreased by m/N. reading means for reading the stored data in units of N bits; and a shift register for holding the same data each time the N-bit data is read from the first storage area of the memory by the reading means, In the first conversion mode, each time the same data is held, the held data is shifted upward by 1 bit, and in the second conversion mode, each time the same data is held, the held data is shifted downward by 1 bit. a first shift register for shifting N times; and a first writing means for writing data after being shifted by one bit in the first shift register to the original storage location of the memory in the first conversion mode; a second shift register into which overflow data from the most significant or least significant bit position of the first shift register is input in series; The data is stored in the second memory of the above memory as a divided character pattern for printing.
a second writing means for sequentially writing into the storage area of the printing pattern converting apparatus.