JPS6133213B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention writes a program into a fixed memory device, and when a problem occurs in the program and a part of the program must be changed or modified, the program can be changed or modified. provides a program modification method designed to make modifications simple and easy.

Generally, when writing a processing program into a fixed memory device, an inexpensive mask ROM (read-only memory) is used. But this ROM
The processing program is fixed by once writing the processing program to the . However, after writing a processing program to the mask ROM in this way, it often happens that a part of the processing program is changed or modified, and in this case, since the program is fixed, a new one is required. It was necessary to replace it with a mask ROM with a program written in it. As a result, when attempting to change or modify a program, it becomes very expensive and it is difficult to make such changes or modifications.

A program modification method proposed to solve these problems will be described below as a reference example.

Figure 1 is a block diagram showing the configuration of a reference example modification method, where 1 is a central processing unit (CPU) and 2 is a mask that permanently stores and holds a processing program.
ROMs 3 and 4 are RAMs (random access memories), of which RAM 3 is the mask ROM.
Mask ROM2 has the same address location as ROM2.
RAM4 stores the changed position of the mask.
It has different addressing from ROM2 and stores the modified program (correction program) in mask ROM2.

To explain in more detail about the RAMs 3 and 4,
First, RAM3 stores the changed position of mask ROM2.
A bit is assigned to each address position to store the presence or absence of a 1-bit change. Therefore, "1" (or "0") is stored in the address position corresponding to the program change location in mask ROM2. The changed position is retained.

On the other hand, since RAM4 has different addressing from mask ROM2, the mask ROM input to CPU1 is placed at the top address position of RAM4.
A processing program is held that searches for a correction program corresponding to an address that requires a program change, and the correction program held in the RAM 4 is selected according to this search process.

5 is a magnetic tape storage device from which data in RAMs 3 and 4 is loaded.

A data bus DB, an address bus AB, and a synchronization signal line CL are connected between the CPU 1, mask ROM 2, RAMs 3 and 4, and magnetic tape storage device 5.

Reference numeral 6 designates a flip-flop that is set in response to the output of the RAM 3, which is set in response to the "1" output from the RAM 3 when the address location of the mask ROM 1 that requires program change arrives, and sends this set output to the CPU 1. This is introduced as an interrupt signal.

To explain a little more about the operation of the modification method based on the configuration shown in FIG. 1, when it is necessary to partially modify the fixed processing program written in the mask ROM 2, first, the address position of the mask ROM 2 that needs to be modified and the correction are made. A program is written in the magnetic tape storage device 5, data is loaded from the magnetic tape storage device 5, and the address position to be changed and the correction program are stored and held in the RAMs 3 and 4, respectively.

In this way, RAM 3 and 4 have a magnetic tape storage device 5.
After writing the fixed program change position and correction program into the mask ROM 2, the processing program in the mask ROM 2 is executed.

In this execution, from CPU1 to mask ROM2
are sequentially addressed, and the programs in the ROM 2 are sequentially accessed and executed.

At this time, since the RAM 3 has the same addressing as the mask ROM 2 and address information is transferred from the CPU 1, it is addressed in a synchronous relationship with the mask ROM 2, and data at that address position is read out. In other words, the RAM 3 stores "0" for program steps that do not require changes and "1" for program steps that require changes, and when there is a "0" output from RAM 3, the flip-flop 6 is reset. It has become a state.

Therefore, the CPU 1 is connected to the flip-flop 6.
The program steps of the mask ROM 2 are sequentially progressed until an interrupt signal, which is the set output of the mask ROM 2, does not arrive.

Now, when the address location of mask ROM2 reaches the address location where the program needs to be changed, RAM3
"1" is output from the flip-flop 6, and the flip-flop 6 is set. The flip-flop 6 detects that it is now at an address location that requires a change, and
Introduce an interrupt signal (set output) to CPU1 and issue an interrupt. The CPU 1 temporarily stores the current address value in response to the interrupt signal.
The starting address of the RAM 4 is selected, an address location for storing a corresponding correction program is searched from the temporarily stored address value, and the program is jumped to this correction program location.

Therefore, the correction program of this RAM 4 will be executed. Further, at the end of this correction program, a jump instruction is stored to again address the next address value of the corrected position in the mask ROM 2, and when this correction program is completed, the program in the mask ROM 2 is executed again.

Furthermore, the program in the mask ROM 2 is executed sequentially, and when an address position that requires change is reached again, the flip-flop 6 is set, an interrupt is issued to the CPU 1, and the correction program corresponding to the address position in RAM 4 is executed. .

However, in such a program change method, RAM3 has the same number of addresses as mask ROM2 and an area indicating the need for a 1-bit program change. was necessary.

The present invention has been made in view of the above-mentioned problems, and is designed to reduce the capacity of the RAM as much as possible by making improvements to the RAM that stores the address locations of whether or not program changes are necessary.

The present invention will be explained in detail below.

FIG. 2 is a block diagram of an embodiment of the present invention, and the main difference from the reference example of FIG.
The main difference is that the RAM is divided into two parts: RAM3A and RAM3B.

The RAMs 3A and 3B are located at upper address positions A ₈ -
A ₁₅ and lower address positions A ₇ to _{A 0} are allocated, and each of these positions A ₈ to A ₁₅ and A ₇ to _{A 0} has a capacity of 4 bits. Therefore, one of RAM3A is
It has a capacity of 256 x 4 bits.

For example, address A ₀ ~ of mask ROM2
A: Assuming that ₁₅ has a 2-block correction program,
And as the address of that one correction block
10 to 15 (OO, OA) to (OO, OF) and 1000 to one correction block address.
1010 (O3, E8) ~ (O3, F2), first store "0001" in code at the (OO) address position of RAM3A regarding the former correction block.
Code “0001” is stored from the (OA) address position to the (OF) address position of RAM3B. Also, for the latter correction block, the code "0010" is stored in the address position (O3) of the RAM 3A, and the code "0010" is stored in the address positions (E8) to (F2) of the RAM 3B. Then, "0000" is stored in all address positions of RAM 3A and 3B other than the above.

In this stored state, the mask ROM 2 is sequentially addressed to access the program and execute its instructions. Then, when the address of the mask ROM 2 reaches the 10th to 15th positions, the code "0001" is output from the RAMs 3A and 3B, and the comparator 7 detects a coincidence between the two outputs, and the flip-flop 6 is set by this coincidence output. be done. The set output of the flip-flop 6 causes an interrupt to the CPU 1, and in response to the interrupt signal, the CPU 1 temporarily stores the current address value, selects the first address of the RAM 4, and reads this address from the temporarily stored address value. The address location storing the corresponding correction program is retrieved and jumped to this correction program location. In this case, following address 10 of mask ROM2, 11, 12, 13, 14,
Similarly to the above, position 15 is also jumped to the correction program in RAM4, and thereafter, starting from address 16, the program in mask ROM2 is executed.

Also, when the address of the mask ROM 2 reaches the 1000 to 1010 position, the code "0010" is output from the RAMs 3A and 3B, and the comparator 7 detects a coincidence between the two outputs, and the flip-flop 6 is set by this coincidence output. Ru. The flip-flop 6
An interrupt is made to the CPU 1 by the output of , and the CPU 1 is jumped to the correction program in the RAM 4 in the same manner as above.

In this embodiment of FIG. 2, a mask is used as described above.
RAM3 that stores the corrected address position of ROM2
The capacity of each of A and 3B can be reduced to 256 x 4 bits.

As described above, the program change method of the present invention is as follows:
It has a fixed storage means (ROM) 2 that fixedly stores a processing program, and an address position corresponding to each address held by the fixed storage means, and the address information of each address position is stored as an upper address (upper address bit). The program is divided into lower addresses (lower address bits) and includes an upper address memory 3A to which each of the upper addresses is assigned and a lower address memory 3B to which each of the lower addresses is assigned, and is stored in the fixed storage means. A readable/writable first memory, in which the same signal indicating program correction is stored at corresponding addresses of the upper address memory and the lower address memory corresponding to the address of the content correction position.
storage means (RAM); and a second readable/writable storage means in which a correction program corresponding to the address of the correction position held in the first storage means is stored.
storage means (RAM) 4, and the fixed storage means,
A central processing unit (CPU) 1 that controls the first and second storage means; when the central processing unit sequentially accesses the fixed storage means and the first storage means to execute the processing program, the central processing unit (CPU) 1 controls the first and second storage means; detection means for detecting whether a program correction signal is simultaneously called from the upper address memory and the lower address memory of the first storage means and introducing an interrupt signal to the central processing unit based on the detection; In response to an interrupt signal from the CPU, the central processing unit searches for the correction program held in the second storage means corresponding to the correction position address at the time of the interrupt, and jumps to the correction program. The capacity of the first storage means for storing the corrected addresses of the processing program need not be very small, and the unique program can be easily and easily changed, and can be done at a low price.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a program changing method of a reference example, and FIG. 2 is a block diagram showing the configuration of the program changing method of the present invention. 1: Central processing unit (CPU), 2: Fixed storage means (mask ROM), 3A: RAM that stores the upper address of the correction address position, 3B: RAM that stores the lower address of the correction address position, 4: Correction program 5: magnetic tape storage device, 6: flip-flop, 7: comparator.

Claims (1)

[Scope of Claims] 1. A fixed storage means (ROM) 2 for fixedly storing a processing program, and an address position corresponding to each address held by the fixed storage means, and address information of each address position is stored in an upper level. It is divided into addresses (upper address bits) and lower addresses (lower address bits), and includes an upper address memory 3A to which each of the above-mentioned upper addresses is assigned and a lower address memory 3B to which each of the above-mentioned lower addresses is assigned; a readable/writable first storage means in which the same signal indicating program correction is stored at corresponding addresses of the upper address memory and the lower address memory corresponding to the address of the correction position of the program content stored in the storage means; (RAM), and a readable/writable second storage means (RAM) 4 in which a correction program corresponding to the address of the correction position held in the first storage means is stored.
a central processing unit (CPU) 1 that controls the fixed storage means, first and second storage means; and a central processing unit (CPU) 1 that controls the fixed storage means and the first and second storage means;
When executing a processing program by sequentially accessing the storage means of the first storage means, it is detected whether a program correction signal is called from the upper address memory and the lower address memory of the first storage means at the same time, and based on the detection, the central a detection means for introducing an interrupt signal into the processing device, and a correction program held in the second storage means corresponding to the correction position address at the time of the interrupt by the central processing unit in response to the interrupt signal from the detection means. A method for changing a program that searches for the corrected program and jumps to the corrected program.