JPS6133215B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operand address determination device, and more particularly, the present invention relates to an operand address determination device, and more particularly, the present invention relates to an operand address determination device that determines whether two operands specified by instruction words readable within an electronic computer overlap within the range of the operand length. The present invention relates to a device that determines whether or not a person is present.

There are various formats of instructions used in electronic computers, but generally, as shown in Figure 1a, an instruction code F that specifies an operation such as addition/subtraction, logical operation, or transfer, and a first Address OA with operand
1, the address OA2 where the second operand is located, and the number of bytes (operand length) L of both operands OP1 and OP2. The number of bytes of the operand is 2 bytes, 4 bytes, 8 bytes, 16
bytes, 32 bytes, etc., and there is no need to specify it if either is fixed by the computer, but if the operand length is not fixed or the first and second operand lengths are If they are different, it is necessary to specify L ₁ and L ₂ respectively.

Now, both operand lengths L ₁ and L ₂ are the same number of bytes, as shown in FIG.
As shown in Figure 1c, both operands OP
1. If OP2 is stored at a duplicate address, special processing must be performed, depending on the type of computer. That is, only the operand portion x that overlaps on the address must be processed one byte at a time.

If operands OP1 and OP2 are not duplicated in the storage device 30, 4-byte machines usually process 4 bytes at a time. For example, when performing addition/subtraction processing, the first operand OP1 and the second operand OP2 are processed by 4 bytes. After reading byte by byte and performing addition/subtraction, the result is sent to the first operand OP1.
is stored at the address where it was stored.

On the other hand, if both operands OP1 and OP2 overlap as shown in Figure 1c, especially at the start address of the first operand OP1, if 4 bytes are processed, After reading and performing addition and subtraction, the result is written to the address where the first operand OP1 was stored, so the contents of the first operand OP1 are changed, and the data of the first operand OP1 is read again in other processing. When issued, data with incorrect contents will be used.

Therefore, the operands OP1, OP
2 is duplicated, and if so, the duplicated parts are processed one byte at a time to prevent the contents from being changed.

Note that in the case of a computer that can only process one byte, no problem will occur even if the data is stored redundantly.

Next, as a method for determining whether or not both operands OP1 and OP2 have an overlapping relationship with each other, conventionally, both operand addresses OA1 and OA
Compare 2 and calculate the difference value (OA1-OA2)
A further comparison operation is performed between and the operand length L, and if the operand length L is larger than the difference value, there is a duplicate.
If it is smaller, it is determined that there is no overlap. That is, as shown in FIG. 2, the arithmetic unit 31 calculates the difference value between both operand addresses OA1 and OA2, then the arithmetic unit 32 subtracts the operand length L and the difference value, and the result is sent to the determination circuit 33. Judge by.

However, in this method, it is possible to make a decision by passing it through the arithmetic unit twice, but it takes one machine cycle to pass through the arithmetic unit 31, one machine cycle to pass through the arithmetic unit 32, and the judgment of the judgment circuit 33. The operation takes one machine cycle, a total of three machine cycles, and the timing at which it can be determined is delayed by the time it takes to pass through the arithmetic unit twice.

Generally, a check for operand duplication is performed at the beginning of an instruction word, but the longer the timing at which the determination can be made is delayed, the lower the performance will be.

The purpose of the present invention is to improve such conventional drawbacks, reduce the number of arithmetic units for determining whether operands are duplicated, speed up the timing at which the determination can be made, and prevent deterioration in computer performance. An object of the present invention is to provide an operand address determination device that can prevent such problems.

The operand address determination device of the present invention comprises two
an arithmetic unit that calculates the difference value between two operand addresses; a difference determination circuit that determines the difference value between the addresses in multiple size steps; and an operand length that determines the specified operand length in multiple size steps. A determination circuit is provided, and a determination circuit is provided that compares the difference value between the operand addresses corresponding to each stage and the magnitude of the operand length, and determines whether or not the two operands overlap each other within the range of the operand lengths. It is characterized by

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an operand diagram illustrating an embodiment of the present invention.
FIG. 2 is a logical configuration diagram of an address determination device.

The operand address determination device shown in FIG. Discrimination circuits 8 and 9 that discriminate the length in stages of the same or different sizes as above, and AND circuits 10, 11, and 12 that correlate the discrimination results with each other and compare the operand length and the difference value. According to
The level of the output terminal 20 is checked to determine whether the operand length is greater than or equal to the address difference value.

In this embodiment, it is assumed that the operand address is 2 bytes (16 bits) and the operand length is 16 bytes or less (represented by 4 bits).

The first address register 1 and the second address register 2 each contain the first operand.
Address OA1 and second operand address OA
2 is set. Arithmetic unit 3 has a first operand address OA1 and a second operand address
Find the difference value (absolute value) of OA2. Difference (16)
The determination circuit 4 determines that the difference value is 16 bytes or less, and the inverter output 13 indicates that there is still a possibility that there is a duplicate even if only this determination is made. The difference (8) determination circuit 5 determines that the difference value is 8 bytes or less, and indicates this with the output 14, and the difference (4) determination circuit 6 determines that the difference value is 4 bytes or less. This is shown in output 15.

A specified operand length is set in the operand length register 7, and in this embodiment, the first operand length is set.
Both operand OP1 and second operand OP2,
Assume that the lengths are equal.

Operand length (8) discrimination circuit 8 and operand length (4) discrimination circuit 9 each have an operand length of 8 bytes,
Or, it determines that it is 4 bytes or less, and outputs 16 or 17 to AND circuits 10 and 11.
to notify.

The 2-input AND circuits 10 and 11 and the 3-input AND circuit 12 determine whether the operand length is less than or equal to the difference value between both addresses.

FIG. 4 is a diagram showing the structure of the difference discrimination circuit in FIG. 3.

Hereinafter, the level of the signal line will be expressed as "H" for high level and "L" for low level.

Pin numbers 0 to 15 are arranged as output terminals of the arithmetic unit 3, and when all pin outputs are "H", the output is ²¹⁷ bytes.

In order to compare with the operand length of 16 bytes,
Values of 16 bytes or more can be ignored in the differential value output.
Therefore, the difference value is determined only when the outputs of the first 12 bits (pin numbers 0 to 11) of the arithmetic unit output are all "L".

When the logical sum of the output signals of bits 0 to 11 is an "L" signal, the output of the difference (16) discrimination circuit 4 is sent to the signal line 13 as an "H" signal by the inverting circuit 41. In this way, the "H" signal is sent to the next-stage AND circuit 12 when the difference value is 15 bytes or less, but it is unclear whether it is 8 bytes or less or 4 bytes or less, and there is still a possibility of duplication. This is to show that their sexuality remains.

Furthermore, if any one of the output signals of bits 0 to 11 has an "H" signal, the output of the differential (16) discrimination circuit 4 is sent as an "L" signal to the signal line 13 by the inverting circuit 41. Ru. In this case, this indicates to the next-stage AND circuit 12 that the difference value is 16 bytes or more and that there is no possibility of duplication.

Similarly, the difference (8) discrimination circuit 5 is an OR circuit of bits 0 to 11 and bit 12 of the arithmetic unit output. If all bits 0 to 11 are “L” and bit 12 is “H”, the remaining bits 13 to 1
When the value of 5 is "111", it is 15, and when it is "000", it is 8, so the difference value is in the range of 8 to 15 bytes. On the other hand, if bits 0 to 11 are all "L" and bit 12 is also "L", the remaining bits 13 to 1 are
Since the value of 5 is 7 when it is "111" and 0 when it is "000", the difference value is in the range of 0 to 7 bytes. In this case, since there is no inversion circuit, "H" is sent to the signal line 14 when the difference value is 8 bytes or more, and "L" is sent to the signal line 14 when it is 7 bytes or less.

In the same way, the difference (4) discrimination circuit 6 detects bits 0 to 11, bits 12, and bits 13 of the arithmetic unit output.
This is an OR circuit. If bits 0 to 12 are all “L” and bit 13 is “H”, the remaining bits 14 and 15 are 7 when they are “11” and 4 when they are “00”, so the difference value is 4 to 12. It is 7 bytes,
If bit 13 is “L”, the remaining bits 14,
Since 15 is 3 when it is "11" and 0 when it is "00", the difference value is 0 to 3 bytes. That is, when the difference value is 4 bytes or more, an "H" signal is sent to the signal line 15, and when it is 3 bytes or less, a "L" signal is sent to the signal line 15.

If the arithmetic unit output indicates 8 bytes, bit 12 will be "H" and bits 0 to 11 and bits 13 to 15 will be "L", so signal line 1
3, 14, and 15 all become "H" signals.

FIG. 5 is a diagram showing the structure of the operand length determination circuit in FIG. 3.

The principle of FIG. 5 is exactly the same as that of the difference discrimination circuit shown in FIG. Note that although the sizes of the stages for determining each stage are divided into 8 bytes and 4 bytes in both FIGS. 4 and 5, they do not need to be the same.

The output of the operand length register 7 represents 16 bytes with 4 bits (bits 0 to 3), and the operand length (8) discriminating circuit 8 detects only bit 0 of these and determines whether it is 8 bytes or more or 7 bytes. The other operand (4) determining circuit 9 detects bits 0 and 1, and determines whether it is 4 bytes or more when it is "0 or 1", or 3 bytes or less when it is "00". The discrimination circuits 8 and 9 each include an inverting circuit 8.
1 and 91 are connected, the signal line 16 is set to "H" when the operand length is 7 bytes or less.
When the operand length is 8 bytes or more, "L" is sent to the signal line 17, and "H" is sent to the signal line 17 when the operand length is 3 bytes or less, and "L" is sent when the operand length is 4 bytes or more.

FIG. 6 is a diagram showing the signal line level state of the embodiment shown in FIG.

Figure 6a shows the case where the difference value is 8 bytes and the operand length is 10 bytes when operands overlap, and Figure 6b shows the case where the difference value is 8 bytes and the operand length is 6 bytes and there is no overlap. It shows.

In the state shown in Fig. 6a, the output of the arithmetic unit shown in Fig. 3 is 8.
Since it shows a byte, the difference discrimination circuits 4, 5,
The signal lines 13, 14, and 15 of No. 6 all become "H". Also, since the operand length is 10 bytes,
Signal lines 16 and 17 of operand length determination circuits 8 and 9
Both become "L". Therefore, signal line 1
3, 18, and 19 all become "H", so the output signal line 20 of the AND circuit 12 becomes "H",
Indicates that it is duplicated.

Next, in the state shown in FIG. 6b, the signal lines 13, 14, and 15 all become "H" as in the previous case. Since the operand length is 6 bytes, the output signal line 16 of the operand length (8) discrimination circuit 8 becomes "H", and the output signal line 1 of the operand length (4) discrimination circuit 9 becomes "H".
7 becomes “L”, so signal lines 13, 18, 19
are "H", "L", and "H", respectively, and as a result, the output signal line 20 of the AND circuit 12 becomes "L", indicating that there is no overlap.

FIG. 7 shows the difference values in the example of FIG. 3, and
FIG. 3 is a diagram showing a determination state of operand duplication in relation to operand length.

Based on the embodiments shown in FIGS. 6a and 6b, the level state of the signal line 20 is expressed in terms of the relationship between the difference value and the operand length, as shown in FIG. 7. In addition, the seventh
In the figure, "H" indicates an overlapping state, and "L"
indicate a non-overlapping state, and "H" levels marked with a circle are determined to be overlapping even though they are logically not overlapping. This is because the structure of the present invention determines the difference value and operand length in stages within 4 bytes, 8 bytes, and 16 bytes. In this case, if it is determined that there is no overlap even though there is logical overlap, it would be a serious problem, but in Figure 7, the opposite is the case, and the circle is marked. In the judgment range,
Although 1 byte processing is performed and the processing speed is slower than usual, the overall calculation operation in the duplication determination can be reduced, so the processing speed can be increased in that respect.

In addition, in FIG. 7, if the operand length is 8 bytes or less or the difference value is 16 bytes or more, there are few ○ marks, so if this range is emphasized, the present invention is extremely effective. Recognize.

Although this embodiment has been described assuming that the operand address is 2 bytes and the operand length is 16 bytes or less, there is no need to limit it in this way, and it does not matter how many bytes they are. Furthermore, the difference discrimination circuit and the operand length discrimination circuit may determine any number of sizes depending on the size.

Furthermore, when the first and second operand lengths are different, the present invention can be applied by providing separate operand length determination circuits.

As explained above, according to the present invention, the difference value between both operand addresses obtained by the arithmetic unit is determined by the difference determination circuit, and the determination circuit compares the difference value in correspondence with the result determined by the operand length determination circuit. Since it is possible to judge whether or not both operands overlap each other within the range of their operand lengths, the number of arithmetic units can be reduced by one compared to the conventional method, thereby speeding up the judgment timing and increasing the computational efficiency. It is possible to prevent performance degradation due to duplication.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the case where operands overlap.
FIG. 2 is a schematic diagram of a conventional operand duplication check circuit, FIG. 3 is a logical configuration diagram of an operand address determination device showing an embodiment of the present invention, and FIG. 4 is a diagram showing the structure of the difference determination circuit in FIG. 3. Figure, 5th
3 shows the structure of the operand length determination circuit in FIG. 3, FIG. 6 shows the signal line level state in the embodiment shown in FIG. 3, and FIG. 7 shows the difference value in the embodiment shown in FIG. FIG. 3 is a diagram showing a determination state of operand duplication in relation to operand length. 1, 2: Operand address register,
3: Arithmetic unit, 4, 5, 6: Difference discrimination circuit, 7: Operand length register, 8, 9: Operand length discrimination circuit, 10, 11, 12: AND circuit, 41, 8
1,91: Inversion circuit.

Claims (1)

[Claims] 1. An arithmetic unit that calculates the difference value between two operand addresses, a difference determination circuit that determines the difference value in multiple size steps, and an operand length that determines the specified operand length in multiple size steps. It is equipped with a determination circuit and a determination circuit that compares the difference value of both operand addresses corresponding to each stage with the magnitude of the operand length, and determines whether or not both operands overlap each other within the range of the operand length. Characteristic operand address determination device.