JPS6133262B2 - - Google Patents
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- Publication number
- JPS6133262B2 JPS6133262B2 JP52156485A JP15648577A JPS6133262B2 JP S6133262 B2 JPS6133262 B2 JP S6133262B2 JP 52156485 A JP52156485 A JP 52156485A JP 15648577 A JP15648577 A JP 15648577A JP S6133262 B2 JPS6133262 B2 JP S6133262B2
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- JP
- Japan
- Prior art keywords
- region
- conductivity type
- metal
- type
- heating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、特に
非整流性接触の良好な電極を設置する半導体装置
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which electrodes with good non-rectifying contact are provided.
半導体装置の電極は、直下の半導体基板との間
で非整流性接触を良好にするため、基板の表層の
不純物密度を内部の不純物密度より高く形成しこ
の表層に設けられた基板表面に形成されている。
例えば、第1図に示すNPNトランジスタは、N-
型基体1の一側表面にコレクタ拡散を行つてN+
型領域2を、また、他側表面にベース拡散を行つ
てP型ベース領域3を形成した後、N+型エミツ
タ領域4と接続用のP+型ベース領域同型高不純
物密度領域5とを同時又は前後に行われる拡散工
程により形成している。6は選択的に形成された
酸化ケイ素層、7はホウ素又はガリウムでよい
族不純物層であり、この拡散には例えば、同時拡
散による場合でも1100〜1200℃で数10分〜数時間
を要している。 Electrodes of semiconductor devices are formed on the surface of the substrate by forming the impurity density on the surface layer of the substrate higher than the impurity density inside the substrate in order to make good non-rectifying contact with the semiconductor substrate immediately below. ing.
For example, the NPN transistor shown in FIG .
Collector diffusion is performed on one side surface of the mold base 1, and N +
After forming the type region 2 and the P type base region 3 by performing base diffusion on the other side surface, the N + type emitter region 4 and the P + type base region same type high impurity density region 5 for connection are simultaneously formed. Alternatively, it is formed by a diffusion process performed before and after. 6 is a selectively formed silicon oxide layer, 7 is a group impurity layer which may be boron or gallium, and this diffusion takes several tens of minutes to several hours at 1100 to 1200°C even when simultaneous diffusion is used. ing.
この発明は電極設置に際し、短時間低温で接続
用の同型で高不純物密度の領域を形成するよう改
良された半導体装置の製造方法を提供するもので
ある。すなわち、この発明は半導体基板の一方の
表面側の一導電型領域表面に電極を設置するにあ
たり、同導電型不純物金属を少くともこの領域表
面に蒸着した後、上記蒸着側表面を反対側表面よ
りやや低温において短時間一次加熱しこの同導電
型不純物となる金属を熱泳動させ、次いで両表面
に対する上記加熱条件を反転させて二次加熱を施
し、遊離金属を基板の表面に還付させることによ
り熱泳動と還付によつて金属が移動した過程に同
導電型高不純物密度領域を形成することを特徴と
する半導体装置の製造方法にある。 The present invention provides an improved method for manufacturing a semiconductor device that forms a region of the same type and high impurity density for connection at a low temperature for a short period of time when electrodes are installed. That is, when an electrode is installed on the surface of a region of one conductivity type on one surface side of a semiconductor substrate, the present invention deposits an impurity metal of the same conductivity type on at least the surface of this region, and then deposits an impurity metal of the same conductivity type on the surface of the region, and then deposits the impurity metal on the surface of the region on the other side. Primary heating is performed for a short period of time at a slightly low temperature to cause the metal that becomes the impurity of the same conductivity type to migrate thermophoretically, and then secondary heating is performed by reversing the heating conditions for both surfaces to return the free metal to the surface of the substrate. A method of manufacturing a semiconductor device is characterized in that a high impurity density region of the same conductivity type is formed in the process of metal movement by electrophoresis and reduction.
このようなこの発明の半導体装置の製造方法に
於ける一次加熱は、例えば蒸着金属層がアルミニ
ウムで、その層厚が数十ミクロン、ケイ素基板厚
さが例えば0.5mmのとき、真空中で蒸着側表面を
690℃に、反対側表面を上記蒸着側表面よりも30
〜50℃高温に設けた加熱炉に数分間経過させるも
のである。 The primary heating in the method for manufacturing a semiconductor device of the present invention is performed by heating the evaporation side in a vacuum when the evaporation metal layer is, for example, aluminum and the layer thickness is several tens of microns, and the silicon substrate thickness is 0.5 mm, for example. the surface
At 690℃, the opposite surface is heated to 30℃ higher than the above vapor deposition side surface.
It is placed in a heating furnace set at a high temperature of ~50°C for several minutes.
次に二次加熱はこの基板を反転させることによ
つて一次加熱と基板に対する加熱条件を反転させ
数分経過させることにより施される。なお、上記
一次加熱での蒸着側表面温度は例えば1300℃まで
の範囲で選択してよく、この場合にも反対側表面
温度は上記温度よりも30〜50℃高温とする。ま
た、蒸着金属が金アンチモン合金であるとき一次
加熱で蒸着側表面温度を1150℃に、反対側表面温
度を1200℃におくとよい。 Next, secondary heating is performed by inverting the substrate, thereby reversing the heating conditions for the primary heating and the substrate, and allowing several minutes to pass. Note that the surface temperature on the vapor deposition side in the above primary heating may be selected within a range up to 1300°C, and in this case also, the surface temperature on the opposite side is set to be 30 to 50°C higher than the above temperature. Further, when the vapor deposited metal is a gold-antimony alloy, it is preferable to set the surface temperature of the vapor deposition side to 1150°C and the opposite side surface temperature to 1200°C during primary heating.
叙上の如く、基板の一方の表面上に被着形成さ
れた不純物となる金属層を蒸着形成し、この蒸着
側表面を他方の表面よりも低い温度で短時間加熱
する一次加熱により、蒸着金属は熱泳動して基板
表層のケイ素結晶中に入るとともに基板の一方の
表面側の一導電型領域と同型の高不純物密度領域
を形成する。そして結晶外に遊離して存在する金
属は二次加熱により蒸着金属面に還付されてケイ
素基板の導電性に関与しない。ただし、熱泳動は
結晶欠陥部分で増速するから、泳動させる領域は
歪がないようにする。 As mentioned above, a metal layer to be an impurity is formed on one surface of the substrate by vapor deposition, and the vapor-deposited metal layer is heated for a short time at a lower temperature than the other surface by primary heating. is thermally migrated into the silicon crystal on the surface layer of the substrate and forms a high impurity density region of the same type as the one conductivity type region on one surface side of the substrate. The metal that exists free outside the crystal is returned to the vapor-deposited metal surface by secondary heating and does not contribute to the conductivity of the silicon substrate. However, since the speed of thermophoresis increases in crystal defect areas, the region to be migrated should be free from distortion.
以下実施例につき第2図および第3図を参照し
て説明する。 Examples will be described below with reference to FIGS. 2 and 3.
第2図でリンが微少添加された比抵抗5Ω−cm
のN-型ケイ素基体1の一方の表面にガリウムを
拡散してP型ベース領域3を、又他側表面にリン
を拡散してN+型コレクタ接続領域2を形成し、
上記P型ベース領域の一部にはリンを選択拡散し
てエミツタ領域4を形成したN+PN-N+トランジ
スタについて、エミツタ領域の一部並びにベース
領域の所望の一部を露出し残部表面を酸化ケイ素
層6で被覆する。ついでアルミニウム蒸着層7を
形成する。このケイ素基板0を炉8に収容し、
10-4〜10-6Torrの真空内でN+型コレクタ接続領
域2に対向する炉壁面81をタングステンヒータ
で加熱してこの壁面を800℃に、一方、蒸着層7
に対向する炉壁面82を水冷してこの壁面を上記
壁面よりも50℃低温の750℃にして約10分間の一
次加熱を施す。 Figure 2 shows a specific resistance of 5Ω-cm with a small amount of phosphorus added.
gallium is diffused on one surface of the N - type silicon substrate 1 to form a P type base region 3, and phosphorus is diffused on the other surface to form an N + type collector connection region 2;
Regarding the N + PN - N + transistor in which the emitter region 4 is formed by selectively diffusing phosphorus into a part of the P type base region, a part of the emitter region and a desired part of the base region are exposed and the remaining surface is exposed. Cover with a silicon oxide layer 6. Then, an aluminum vapor deposition layer 7 is formed. This silicon substrate 0 is placed in a furnace 8,
In a vacuum of 10 -4 to 10 -6 Torr, the furnace wall surface 81 facing the N + type collector connection region 2 is heated to 800° C. by heating this wall surface with a tungsten heater.
The furnace wall surface 82 facing the above is cooled with water, and this wall surface is heated to 750.degree. C., which is 50.degree. C. lower than the above-mentioned wall surface, and primary heating is performed for about 10 minutes.
次にケイ素基板配置を上下反転させることによ
つて加熱条件を反転させ、即ち蒸着面が炉内高温
側にあるようにして10分間経過させる二次加熱を
行なう。 Next, the heating conditions are reversed by turning the silicon substrate upside down, ie, the deposition surface is placed on the high temperature side of the furnace, and secondary heating is performed for 10 minutes.
上記アルミニウム蒸着層7は選択蝕刻を施して
第3図に示すようにエミツタ領域4の表面にエミ
ツタ電極9として残置できる。また、同時にP型
ベース領域表面には非整流接触を良好にするよう
にP+型高不純物密度領域10が熱泳動により形
成される。なお、この例でN+エミツタ領域は1
〜2桁程度高濃度であるためにアルミニウムの熱
泳動によつて導電型が左右されることはない。 The aluminum vapor deposited layer 7 can be selectively etched and left as an emitter electrode 9 on the surface of the emitter region 4, as shown in FIG. At the same time, a P + type high impurity density region 10 is formed on the surface of the P type base region by thermophoresis so as to improve non-rectifying contact. Note that in this example, the N + emitter area is 1
Since the concentration is about two orders of magnitude higher, the conductivity type is not affected by aluminum thermophoresis.
次に、予定領域表面がN型であるとき、アルミ
ニウムに代えて金アンチモン合金を蒸着しこの発
明の製造方法を実施すると、高不純物密度領域の
N+型領域が形成される。 Next, when the surface of the planned region is N-type, if a gold-antimony alloy is deposited instead of aluminum and the manufacturing method of the present invention is carried out, the high impurity density region
An N + type region is formed.
叙上の如く、本発明によれば従来の高不純物密
度領域が拡散で形成される場合よりも200〜300℃
も低温で、かつ数時間が必須であつたものが、数
分に短縮された。しかも再現性良く所望領域を形
成できる顕著な利点がある。 As mentioned above, according to the present invention, the temperature is lowered by 200 to 300°C than when the conventional high impurity density region is formed by diffusion.
What used to require several hours at low temperatures has now been reduced to just a few minutes. Moreover, it has the remarkable advantage of being able to form a desired area with good reproducibility.
第1図は従来の方法によりP+型ベース領域同
型高不純物密度領域が形成されたN+PN-N+トラ
ンジスタの断面図、第2図はこの発明の製造方法
の一実施例につき一次加熱工程にあるN+PN-N+
トランジスタ半成品の断面図、第3図はこの発明
の一実施例により形成されたN+PN-N+トランジ
スタの断面図である。
0……半導体基板(ケイ素基板)、7……(金
属)蒸着層、10……高不純物密度領域、81…
…高温の炉壁面、82……低温の炉壁面。
FIG. 1 is a cross-sectional view of an N + PN - N + transistor in which a high impurity density region of the same type as the P + type base region is formed by a conventional method, and FIG. 2 shows a primary heating step in an embodiment of the manufacturing method of the present invention. N + PN - N +
FIG. 3 is a cross-sectional view of an N + PN - N + transistor formed according to an embodiment of the present invention. 0 ... Semiconductor substrate (silicon substrate), 7... (Metal) vapor deposition layer, 10... High impurity density region, 81...
...High temperature furnace wall surface, 82...Low temperature furnace wall surface.
Claims (1)
面に電極を設置するにあたり、同導電型不純物と
なる金属を少くともこの領域表面に蒸着形成した
後、上記蒸着側表面を反対側表面よりやや低温に
おいて短時間一次加熱しこの同導電型不純物とな
る金属を熱泳動させ、次いで両表面に対する上記
加熱条件を反転させて二次加熱し遊離金属を還付
させることにより同導電型高不純物密度領域を形
成することを特徴とする半導体装置の製造方法。1. When installing an electrode on the surface of a region of one conductivity type on one surface side of a semiconductor substrate, after vapor-depositing a metal serving as an impurity of the same conductivity type at least on the surface of this region, The metal constituting the impurity of the same conductivity type is thermally migrated by primary heating at a low temperature for a short period of time, and then the above-mentioned heating conditions for both surfaces are reversed and secondary heating is performed to reduce the free metal, thereby forming a high impurity density region of the same conductivity type. 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15648577A JPS5489477A (en) | 1977-12-27 | 1977-12-27 | Production of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15648577A JPS5489477A (en) | 1977-12-27 | 1977-12-27 | Production of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5489477A JPS5489477A (en) | 1979-07-16 |
| JPS6133262B2 true JPS6133262B2 (en) | 1986-08-01 |
Family
ID=15628781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15648577A Granted JPS5489477A (en) | 1977-12-27 | 1977-12-27 | Production of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5489477A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753933A (en) * | 1980-09-18 | 1982-03-31 | Toshiba Corp | Manufacture of semiconductor element |
-
1977
- 1977-12-27 JP JP15648577A patent/JPS5489477A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5489477A (en) | 1979-07-16 |
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