JPS6133392B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio notification watch with an alarm that notifies alarm information by voice, and in particular, alarm information including the time is selected and notified by voice as time passes, and when the audio notification is made, The time confirmation and the time elapsed since the set alarm time can be clearly recognized step by step by different notification contents.

2. Description of the Related Art Some conventional alarm clocks use a simple electronic sound to notify that the alarm time has arrived, and thereafter repeatedly sound the electronic sound at predetermined intervals. However, with these devices, you cannot tell what time the alarm is set, and even if the beep sounds at predetermined intervals, you cannot tell how much time has passed.
Also, it is unclear what the current time is, etc.
It had very little practical effect.

The present invention overcomes these conventional drawbacks and provides a useful timepiece with improved alarm effectiveness.

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, when the alarm time (which can be set up to the minute) is reached, a voice is first announced as "Goyoteino 〇〇ji〇〇fundes," and then a melody such as ``For Elise'' is voiced. One minute after the alarm time, a voice announcement of "〇〇ji〇〇fundeskara oisogikudasai" and a melody such as "Troika" will be made, and one minute after that, the same "〇〇ji〇〇fundeskara" will be announced.
For example, a melody such as ``Heaven and Hell'' is announced by voice.

FIG. 1 is a block diagram of a main part of an alarm-equipped audio notification clock according to an embodiment of the present invention.

RU is an instruction storage circuit (program memory) consisting of read-only memory, RAR is an address register, RDC is an address decoder, and RUG is an instruction selection gate. IM is an instruction decoder that generates micro-orders according to the contents read from the program memory RU via the instruction selection gate RUG. RM is a memory unit consisting of a random access memory that temporarily stores each data to be broadcast, AC is an address counter, AD is an address decoder, MS is an input/output control circuit, FA is an adder that counts up the address counter AC, and ACR. is a reset circuit that resets the AC. ACC is the accumulator, GA is the input gate of the accumulator ACC,
OB is the output buffer and GO is its input gate. JRC is a determination circuit that determines whether the data transferred to the accumulator ACC has a transfer end code EC. The transfer end code EC will be explained in detail later.

CG is a clock generator, DV is a frequency divider,
Outputs a reference signal for measuring time. C.O.
is a clock counter, S indicates the second digit, M indicates the minute digit, and H indicates the hour digit. AR is a register that stores an alarm time, and an arbitrary alarm time is set through a suitable input means (not shown here), such as a key input circuit having various keys.
JS is a discrimination circuit that determines whether the content of the second digit S is 0 or not, and JA _l is a coincidence detection circuit that detects coincidence between the minute digit M and hour digit H of the clock counter CO and the alarm time register AR.

FA _l is a flip-flop that is set by the match detection output of the match detection circuit JA _l , and this set state is judged by the discrimination circuit JF. TK is a key that instructs to stop broadcasting alarm information, and when this key is operated, the flip-flop _FA1 is forcibly reset via the OR gate OR. C is a counter that counts the number of alarm information broadcasts, CR is its reset circuit, and JC is a discrimination circuit that determines whether the count is 0, 1, or 3.

VCC is the audio output control circuit, SP is the speaker,
Audio is output according to the data input via the output buffer OB. The details of the audio output control circuit VCC are as shown in the block diagram of FIG.

VR is a memory unit consisting of read-only memory that stores audio quantized data.
VAC is an address counter and VAD is an address decoder. CLA is a reset circuit that resets the address counter VAC when no audio is output, so that it does not specify any address in the memory unit VR. FA is address counter
This is an adder for incrementing the address of VAC by one step, and the initial address of any audio area P is added to the address counter in order to output audio.
If set to VAC, it will automatically perform VAC + 1 → VAC at a constant sampling frequency from then on.
The electronic data of the corresponding area P is read out sequentially.

CC is a code conversion circuit which inputs the audio area designation signal _S1 supplied from the output buffer OB and converts it into a code for setting the initial address of the audio area P to be output in the address counter VAC. JE was formed at the final step of each region P
The END code detection circuit detects the END code, and this output operates the reset circuit CLA to reset the address counter VAC.
This output is also input as signal S ₂ to the instruction selection gate RUG as shown in FIG.
Operates to set the next initial address.

DAC is a digital-to-analog (D-A) conversion circuit, LPF is a low-pass filter, DD is a speaker drive circuit, and SP is the aforementioned speaker.

The operation will be explained with reference to the flowchart in FIG.

Flip-flop FA _l by discriminator circuit JF at n ₁
is set. Each minute digit M of the clock counter CO and alarm time register AR
If the contents of the hour digit H and the contents of the hour digit H match, the match detection circuit
JA _l detects this and flip-flops
FA _l is set. Once the flip-flop _FA1 is set, the program proceeds to _n2 , generates a micro-order, operates the reset circuit CR, and resets the counter C, which counts the number of alarm information notifications, to 0.

n ₃ , the content of counter C is 0 by the discrimination circuit JC.
Since this is immediately after the counter C has been reset, it is determined that it is 0, and the process proceeds to _n4 . n ₄
Then, the word data string _A1 is transferred to the memory unit RM. As will be described later, when the counter C counts up and reaches 1, the process proceeds from _n3 to _n15 , where it is determined that it is 1, and then proceeds to _n16 , where the word data string _A2 is stored in the memory unit RM. will be forwarded to. When the counter C is further incremented and reaches 2, the process advances to _n17 via _n3 and _n15 , and the word data string _A3 is transferred to the memory unit RM.

The transfer of each word data string A ₁ , A ₂ , A ₃ is as shown in FIG.
As mentioned above, melody ₁ of A1 corresponds to "For Elise," melody 2 of word data string _A2 corresponds to "Troika," and melody ₃ of word data string A3 corresponds to "Heaven and Hell." A more detailed explanation is as follows.

First, a micro order is generated in the first _m1 , and the reset circuit ACR is operated to reset the address counter AC to 0. This specifies the initial address of the data to be transferred in the memory unit RM. Then, each word data such as "Goyotei" (including each word data in the melody) is transferred according to the flowchart in Figure 5a, and each numerical data of the hour digit H and minute digit M is transferred according to the flowchart in Figure 5b. Ru. In the case of word data, as shown in Figure 5a, a micro-order is generated at _P1 and the input gate is
Transfer the word data WD stored in the program memory RU to the accumulator ACC via the GA,
Next, a micro order is generated at _P2 and transferred to the memory unit RM via the input/output control circuit MS, and a micro order is generated at _P3 , and the adder FA is operated to increment the address counter AC by one. Prepare for data transfer. In the case of numerical data, as shown in b in the same figure, a micro order is generated in P ₁ and the contents of the time H or minute digit M are transferred to the accumulator ACC, and then the process goes through P ₂ and P ₃ similar to a above. Numerical data is a memory unit
It is transferred to RM, and the address counter AC is incremented by one. In this way, each word data and numerical data are sequentially stored in the memory unit.
After being transferred to RM, transfer end code in the last me
EC is transferred to memory unit RM. Note that the transfer flow of this code EC is the same as that in FIG. 5a.

Returning to the flowchart of FIG. 3, the explanation will be continued.

When the transfer of the word data string _A1 is completed, the process proceeds to _n5 , a micro order is generated, and the address counter AC is reset again for subsequent read control. Step _n6 determines the set state of flip-flop _FA1 , and unless flip-flop _FA1 is reset by operating key TK during the process, the program will proceed to the next _{step n7} . _n7 determines whether the signal _S2 is output from the audio output control circuit VCC, that is,
In the audio output control circuit VCC shown in FIG. 2, the discrimination circuit JE determines whether or not the END code of _each audio area P is detected. If so, proceed further to n ₈ . _n8 generates a micro order, reads word data from the memory unit RM, and transfers it to the accumulator ACC. _n9 is for determining whether the word data transferred to the accumulator ACC is the transfer end code EC,
If the transfer end code is not EC, proceed to _n10 , generate a micro order, and further transfer the word data to the output buffer OB via the input gate GO.

In the audio output control circuit VCC (see Figure 2),
According to the transferred word data, one audio area P for storing the quantized data of the corresponding word is designated, and audio is output by sequentially reading out this area P.

_n11 designates the next read address of the memory unit RM, generates a micro order, increments the address counter AC by one, and then returns to _n6 . The above-mentioned step _n7 is a step of waiting until one word data is actually outputted as a voice, and the process proceeds to the next _{step n8} only after the voice output of one word data is finished. In this way, steps n ₆ to n ₁₁ are repeated until the transfer end code EC is detected at n ₉ , and each word data is sequentially output as voice. This means, for example, that first the word data string _A1 is transferred to the memory unit RM and read out, so that
〇〇〇〇〇fundes'' followed by Melody's ``For Elise''.

If the transfer end code EC is detected, the process proceeds to _n12 , a micro order is generated, and the counter C is counted up by one. At n ₁₃ , the content of counter C is 3
If it is not 3, the process proceeds to _n14 , where the determining circuit JS determines whether the contents of the seconds digit S are 0 or not. If it is determined to be 0, the process returns to _n3 and the contents of the counter C are determined. n ₁₄ is for starting notification of alarm information only when 00 seconds have passed, and if audio output corresponding to word data string A ₁ etc. is to be performed within 1 minute, from the alarm time. Audio output will be restarted every minute.

If the content of counter C is 1, start from n ₃ .
Proceed to n ₁₅ , this is determined at n ₁₅ , and further proceed to n ₁₆ .
At _n16 , the word data string _A2 is transferred to the memory unit RM as described above. Of course, the contents of the hour digit H and minute digit M have changed at this time. The rest is as explained above, and the second alarm information is “〇〇J〇〇Fundescara.
"Oisogikudasai," followed by Melody's "Troika." Word data string A ₂ with n ₉
When the transfer end code EC is detected and the counter C is counted up further at _n12 , the content of the counter C becomes 2 and the process proceeds to _n17 via _n13 , _n14 , _n3 , and _n15 . At _n17 , the word data string _A3 is transferred, and in the same manner, the third alarm information is "〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇　, followed by the melody's ``heaven and hell'').

At _n9 , the transfer end code EC of the word data string _A3 is detected, and at _n12 , when the counter C is further counted up, its content becomes 3. Therefore the next n ₁₃
Then, it is determined that the number is 3, and the process proceeds to n ₁₈ . n ₁₈ generates micro-order and flip-flop FA _l
and complete the series of operations. In addition,
If you operate TK to reset flip-flop FA _l between the alarm time and the end of the third alarm information voice notification, this will be determined in n ₆ and subsequent operations will be interrupted at any time. Similarly, the series of operations can be terminated. This interruption is possible even during any audio output because when the signal _S2 is not output at _n7 , the process returns to _n6 to determine the set state of the flip-flop _FA1 .

As described above, the present invention provides audio notification of alarm information that changes over time, including the time.By including the time, the time of each audio notification can be confirmed sequentially, and different notification contents can be confirmed. Therefore, it is possible to clearly recognize the passage of time from the set time in sequence, and it is possible to provide a clock that has a higher practical effect than conventional alarm clocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main part showing one embodiment of the present invention, FIG. 2 is a block diagram showing the main part of FIG. 1 in more detail, FIG. 3 is a flowchart explaining the operation, and FIG. A flowchart illustrating a word data string, and FIGS. 5a and 5b are flowcharts illustrating the main operations in more detail. RU...Program memory, RUG...Instruction selection gate, IM...Instruction decoder,
RM...Memory unit, MS...I/O control circuit, GA...Input gate, ACC...Accumulator, CO...Clock counter, AR...Alarm time register, JA _l ...Coincidence detection circuit, C... ...Notification count counter, VCC...Audio output control circuit, SP...Speaker.

Claims (1)

[Claims] 1. means for measuring time, means for detecting coincidence between a preset alarm time and the measured time, means for audibly announcing alarm information including the measured time according to the coincidence detection, and the coincidence detection. A voice with an alarm, comprising: means for selecting alarm information with different contents according to the elapsed time; and means for notifying the alarm information selected by the alarm information selection means. Alarm clock.