JPS6134100B2 - - Google Patents

Description

Detailed Description of the Invention This invention quickly identifies and determines the carrier frequency of an input signal having a temporally discontinuous waveform including pulse modulation or a continuous input signal, and obtains a digital output corresponding to the corresponding frequency. The present invention relates to a digital output frequency measurement receiver for use in a digital output frequency measurement receiver.

A conventional device of this type is shown in FIG.

In Figure 1, 1 is a high frequency signal input terminal, 2
3 and 4 are band-pass filters for determining the frequency to be measured; 3 and 4 are high-frequency signal distribution circuits that distribute high-frequency signals to the subsequent I/Q phase discrimination circuit 6;
5c is a delay circuit for shifting the phase of the input signal in proportion to its frequency; 6 is a delay circuit for phase-combining the input signal and the input signal delayed by the delay circuits 5a to 5c, detecting the phase difference between the two signals; An I/Q phase discrimination circuit outputs I/Q video outputs having proportional video amplitudes and having phases different by 90 degrees from each other. 7 is a positive/negative discrimination slicer circuit that discriminates whether the output of the I/Q phase discrimination circuit 6 is positive or negative. .

The circuit shown in FIG. 1 is constructed in parallel with frequency measurement receiving circuits CH ₁ to CHn of the first to nth channels.

Further, FIG. 2 shows an example of the I/Q phase discrimination circuit 6.

In Fig. 2, 4 is an in-phase 2-distribution circuit, 21 is a 0°/90° hybrid circuit, 22 is a termination circuit,
23a to 23d are detection circuits with uniform characteristics, and 24 is a differential amplifier circuit.

Next, the operation will be explained.

In FIG. 1, a high frequency signal input to an input terminal 1 is equally distributed in phase to the first channel to the nth channel CH ₁ to CHn by the distribution circuit 3.
The first channel will be explained below. In FIG. 2, it is assumed that the distributed high frequency signal 15 is expressed by V _A (t)=Psinωt. On the other hand, the high frequency signal 16 passing through the delay circuit 5a having a delay time τ becomes V _B (t) = Psinω (t + τ), and the difference is θ = 2πfτ (f is the carrier frequency of the high frequency input signal) with respect to V _A (t). There will be a phase difference. Both signals are input to the I/Q phase discrimination circuit 6.
are phase-combined with each other and detected, V ₁ = 1/2 kP ² (1 + cos θ) = K/2 (1 + cos θ) (1-1) V ₂ = 1/2 kP ² (1- cos θ) = K/2 (1- cosθ) (1-2) V ₃ = 1/2kP ² (1+sinθ) = K/2 (1+sinθ) (1-3) V ₄ = 1/2kP ² (1-sinθ) = K/2 (1-sinθ) It is well known that (1-4).

However, k is the detection circuit efficiency including circuit loss, and K
= kP ² .

Further, the outputs V ₁ to V ₄ are converted by the differential video amplifier circuit 24 into I=Kcosθ and Q=Ksinθ to obtain sinusoidal curves I and Q with a period determined by the input carrier frequency, as shown in FIG. If the polarity of this output video is quantized using the positive/negative discrimination slicer circuit 7 shown in FIG. You can get the divided output.

Similarly, the delay time from the second channel CH ₂ to the n-th channel CHn _is
Compared to , if it is multiplied by 2, 4, 8, ......, 2 ^n-1, the quantized output of the n-th channel is obtained by dividing the frequency of the reciprocal 1/τ of the delay time τ into 2 × 2 ^n-1 equal parts. You can get the output.

FIG. 4 shows a combination of I/Q quantization outputs in a 3-channel configuration. In Figure 4, “1” is the third
The figure shows the case where the I/Q video outputs are each of positive polarity, and "0" shows the case of negative polarity. 1st channel, and 3rd channel (n channel in case of n channel)
For the second channel (n channel), the I/Q output is used together, and for the second channel (n channel), the second
For all channels from the channel to the (n-1)th channel, only the I output is used as shown in FIG. 4, forming a total of 5 bits of output data.
As a result, as shown in the truth table of FIG. 4, bit outputs corresponding to each divided band are obtained, and by performing code conversion, frequency measurement results can be obtained with predetermined digital outputs. However, if each circuit has extremely wideband characteristics, the same digital output will be obtained repeatedly at I/τ, so a bandpass filter 2 is used at the input of this device to determine the band to be measured. It is necessary to enter In the truth table of FIG. 4, the symbol "-" means that the bit output is not used.
This is because the shaded area in Figure 4a is
This is an ambiguous region where the output of the positive/negative discrimination slicer circuit 7 may output both "1" or "0", and if this bit is used in the first channel and the second channel, a large frequency measurement error will occur. This is because there is a possibility that this bit may be used, and it is not particularly necessary to use this bit to obtain frequency measurement results. 2
Increase the delay time after the channel by 2, 4, 8 times...
It is said that ).

However, it is inevitable that an error occurs in the minimum frequency division accuracy due to the third channel.

Since the conventional apparatus is constructed as described above, a large-scale construction is required in order to obtain a high-resolution digital output. Furthermore, since the range of the ambiguous region is determined by the precision of the delay time of the delay line and the precision of the I/Q phase discrimination circuit, there is a drawback that the number of channels cannot be increased unless the precision is made stricter. In the case of a receiver, when considering the influence of noise, the ambiguous area further expands, but in terms of the frequency range, the ambiguous area expands in proportion to the reciprocal of the delay time of each channel, so the delay time If the S/N ratio is insufficient in a short channel (channel with a large weight of 1 bit), a large error will occur, which limits the ability to increase the number of channels and increase the resolution.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and the delay time after the second channel is, for example, 4,
16, 64, ......2 ²ⁿ times or 8, 64, 512, ......
By multiplying by 2 ³ⁿ times, ambiguous areas that appear in the digital output generated at this time are corrected between each channel, and by stacking these, the ambiguity is eliminated, and a stable digital output can be obtained with a simple configuration. It is an object of the present invention to provide a digital output frequency measuring receiver which is very practical as it allows the number of stages and delay time to be freely determined.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 5, the same symbols as in FIG. 1 indicate the same components as in FIG. 1, and 5a, 5c, and 5e are delay circuits with delay times τ, 4τ, and 16τ, respectively. 8 is
A positive/negative discrimination slicer circuit 9 discriminates the positive/negative of the IQ video addition signal (I+Q), a positive/negative discrimination slicer circuit 9 discriminates the positive/negative of the IQ video subtraction signal (I-Q), 10 four positive/negative discrimination slicer circuits 8,
This is a logic circuit that determines the final data based on the outputs of channels 7, 7, and 9 and the correction signal from the channel one step below, which has a long delay time. 11 is a video addition circuit that adds the outputs V ₁ , V ₂ or V ₃ , V ₄ of the high-frequency signal distribution circuit 4; 12 is a slicer circuit that quantizes the video signal after the addition; 13 is a video addition circuit that adds the output signals of the slicer circuit 12; 14 is a 7-bit output of the latch circuit 13.

The circuit shown in FIG. 5 is composed of frequency measurement receiving circuits CH ₁ to _{CH 3} of the first to third channels.

Next, the operation will be explained.

In FIG. 5, the high frequency signal input to the input terminal 1 is sent to the first channel to the third channel by the distribution circuit 3.
In-phase distribution to channels.

The first channel will be explained below.

The distributed high frequency signal is sent to the I/Q phase discrimination circuit 6.
are mutually phase synthesized and detected by
Further, the signal is differentially amplified by the differential video amplifier circuit 24 in the circuit 6, so that I=Kcosθ and Q=Ksinθ. As explained in the conventional operation, the outputs I and Q are periodic functions with a period of 1/τ as shown in FIG.

This IQ video output, and its addition output (I
+Q), the subtraction output (I-Q) is determined by the positive/negative discrimination slicer circuits 7, 7, 8, 9, and quantized, the frequency of the reciprocal 1/τ of the delay time τ of the delay circuit 5a can be divided into 8. I can do it. This conceptual diagram is shown in FIG. That is, this Fig. 6 is a representation of Fig. 3 converted into polar coordinates, but when I and Q are set as the horizontal and vertical axes, the coordinate quadrant is on the left side of Fig. 6b. It corresponds to the conditions of I and Q shown in Figure b, and when I-Q and I+Q are taken as the horizontal and vertical axes, the '' to '' quadrants of the coordinates correspond to the I-Q shown on the right side of Figure b. , I+Q, and as a result, the video output I obtained from the positive/negative discrimination slicer circuits 7, 7, 8, 9,
Based on the results of determining whether Q, I+Q, and I-Q are positive or negative, each video output I, Q is within the eight angle ranges A to H in Figure 6a
It is possible to determine which category it belongs to.

Similarly, the second and third channels CH ₂ , CH ₃
Quadrant discrimination is also performed for . Here, the first and second
Regarding channels CH ₁ and CH ₂ , large measurement errors may occur due to ambiguity in the ambiguous region near the boundaries of the quadrants, so in order to eliminate this ambiguity, the results of the second channel are replaced with the results of the third channel, By correcting each of the first channel with the results of the second channel and accumulating them to eliminate ambiguity, stable digital output can be obtained with the division accuracy of the third channel (the n-th channel in the case of an n-channel). be able to. This conceptual diagram is shown in FIGS. 7 and 8.

In FIG. 7a, the shaded area corresponds to the third and fourth quadrants of the third channel. This shaded area is defined as the range of ambiguity in the second channel, and the final (after correction) output of the second channel is determined as shown in FIG. However, in FIG. 8, when the output of the third channel is in the second quadrant, the output of the second channel is output as is. Similarly, the first
The output of the channel is also the output of the second channel (the third
2 bits from the first channel (divided into 4), 2 bits from the 2nd channel (divided into 4), and 2 bits from the 3rd channel (in the case of n channel) There is no need to correct this from the nth channel), so a digital output of 3 bits (8 divisions), a total of 7 bits (128 divisions) is obtained.

Then, the output V ₁ , V ₂ or
By adding V ₃ and V ₄ , a signal having a constant amplitude with respect to the input frequency is obtained as seen from equations (1-1) to (1-4), and this is processed by the slicer circuit 12 to a predetermined S/ By quantizing the signal in N and latching the digital output of the logic circuit 10 of each channel with the quantized signal to obtain the bit output 14 corresponding to the divided band of 7 bits in total, the frequency measurement result can be expressed as a digital output. Obtainable.

In the above embodiment, a case where the configuration is three channels has been described, but the present invention can be applied to any receiver having a plurality of channels, and the same effects as in the above embodiment can be obtained. It is also possible to latch the digital output by obtaining a synchronizing signal from outside.

As described above, according to the digital output frequency measurement receiver according to the present invention, ambiguous areas that appear in the digital output of each channel are corrected between each channel, and ambiguity is corrected by accumulating the ambiguous areas. Since it is possible to obtain a stable digital output without eliminating the need for a digital signal, it is possible to obtain a device with higher accuracy than the conventional one, and a device with the same accuracy can be made at a lower cost because the number of channels can be reduced. Another advantage is that the number of channels can be increased freely.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional digital output frequency measurement receiver, and Figure 2 is the I/Q in Figure 1.
A detailed circuit diagram of the phase discrimination circuit 6, FIG. 3 is a frequency characteristic diagram of the output voltage to explain the operation of the I/Q phase discrimination circuit, and FIG. 4 is a diagram showing how the circuit of FIG. 1 obtains a digital output. , FIG. 5 is a block diagram of a digital output frequency measurement receiver according to an embodiment of the present invention, FIG. 6 is a conceptual diagram illustrating a method for performing quadrant determination of the logic circuit of FIG. 5, and FIGS. This figure is a conceptual diagram illustrating a method of correcting the output of each channel of the circuit of FIG. 5. 5a, 5b, 5c...Delay circuit, 6...I/Q
Phase discrimination circuit, 7, 8, 9... Positive/negative discrimination slicer circuit, 10... Logic circuit, CH ₁ to CH ₃ ... 1st
~Third frequency measurement receiving circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A delay circuit whose delay time varies from channel to channel and shifts the phase of an incoming input signal in proportion to its frequency; and a signal phase-shifted by this delay circuit and the above-mentioned incoming input signal. an I/Q phase discrimination circuit which outputs I and Q videos having video amplitudes proportional to the phase difference between both signals and whose phases are different from each other by 90 degrees; , a positive/negative discrimination circuit that discriminates whether the addition or subtraction signal of the Q video output is positive, negative, or both outputs, and another series of logic with a longer delay time between the output of this positive/negative discrimination circuit and the delay circuit described above. a plurality of series of frequency measurement receiving circuits each including a logic circuit that determines a final frequency measurement result from the output of the circuit, each series having the delay time described above that differs by an integer multiple, and each logic circuit having a length longer than its own series; When the I video output of a series having a delay time is positive, the output of the positive/negative discrimination circuit of the series having a delay time longer than that of the own series is determined using the output of the positive/negative discrimination circuit of the series having a longer delay time than the own series, and the output is determined. A digital output frequency measurement receiver featuring: