JPH0481144B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION This invention relates to a digitized instantaneous frequency measuring device for rapidly measuring the carrier frequency of continuous wave and pulse modulated high frequency input signals.

[Prior art]

A conventional device of this type is shown in FIG. In Fig. 1, 1 is a high frequency signal input terminal, 2 is a bandpass filter for determining the frequency band to be measured, 3 is an n distribution circuit for distributing the high frequency signal, 4a is a 2-divider, and 5a is a delay time τ. Delay circuit 5b is a delay circuit with a delay time of 2τ, 5c is a delay circuit with a delay time of 2n ^-1 ·τ, 7 is a zero cross slicer circuit that quantizes the output of the I/Q phase discrimination circuit 6a, 8 is a sampling pulse generation circuit 12a
A latch circuit temporarily stores the quantized output of the zero-cross slicer circuit 7 using a sampling pulse synchronized with the high-frequency input signal created by 9. A latch circuit 9 stores the digital output of each latch circuit 8 as a frequency measurement result in the form of, for example, a binary digital code. A digital output circuit that converts and outputs 14
is its output terminal.

As is clear from FIG. 1, the circuit from distribution circuit 4a to latch circuit 8 has a plurality of parallel channels. In addition, as a common part of each channel,
10 is a circuit for detecting and amplifying a high frequency input signal; 1
1 is a slicer circuit that compares and quantizes the video output with reference to the voltage applied to the reference voltage input terminal 13; 12a is a slicer circuit that obtains the arrival timing of the input signal from the quantized output and generates the above-mentioned sampling pulse with a fixed standard; This is a sampling pulse generation circuit.

Further, FIG. 2 shows an example of the I/Q phase discrimination circuit 6a. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. 20 is an in-phase two-way distribution circuit, 21 is a 0°/90° hybrid circuit, 22 is a termination circuit, 23a to 23d are detection circuits with uniform characteristics, and 24 is a differential video amplifier circuit.

Next, the operation of the prior art will be explained.

In FIG. 1, a high frequency signal inputted to an input terminal 1 is equally distributed in phase to the first channel to the nth channel by the n distribution circuit 3 and the two distribution circuit 4a. The first channel will be explained below. In FIG. 2, it is assumed that the distributed high-frequency input signal 15 is expressed by V _A (t)=Psinωt. On the other hand, the high-frequency signal 16 that has passed through the delay circuit 5a having a delay time τ becomes V _B (t) = Psinω (t + τ), and has a phase difference of 2πτ (where is the carrier frequency of the high-frequency input signal) with respect to V _A (t). will have. These two signals are phase-combined and detected by the I/Q phase discrimination circuit 6a, and V ₁ = 1/2k・P ²・(1+cosθ)=K/2(1+cosθ
) V ₂ = 1/2k・P ²・(1−cosθ)=K/2(1−cosθ
) V ₃ = 1/2k・P ²・(1+sinθ)=K/2(1+sinθ
) V ₄ = 1/2k・P ²・(1-sinθ)=K/2(1-sinθ
) is well known.

However, k is the efficiency of the detection circuit including circuit loss, and K=k·P ² .

Further, the outputs V ₁ to V ₄ are converted by the differential video amplifier circuit 24 into I=Kcosθ, Q=Ksinθ, where θ=2πτ, and are converted into sinusoidal curves I, Q proportional to the input carrier frequency as shown in FIG. get. If the polarity of this output video is determined around 0V using the zero cross slicer circuit 7 in Figure 1 and quantized, we get
The frequency range of one period corresponding to the reciprocal (1/τ) of the delay time of the delay circuit 5a can be equally divided into two.

Similarly, the delay time from the second channel to the nth channel is twice that of the first channel.
If it is multiplied by 4 times, 8 times...2 ^n-1 times, the quantized output of the n-th channel will divide the frequency range of the reciprocal (1/τ) of the delay time τ into 2×2 ^n-1 equal parts.

FIG. 4 shows a combination of I/Q quantization outputs in a 3-channel configuration. In FIG. 4, "1" indicates the case where the 1/Q video outputs in FIG. 3 are each positive polarity,
“0” indicates negative polarity. The I/Q outputs are used together for the first channel and the third channel (the n-th channel in the case of an n-channel configuration), and the For all channels), only the I output is
The combinations shown in the figure are used to form a total of 5 bits of output data. As a result, as shown in the truth table of FIG. 4, bit outputs corresponding to each divided band are obtained, code conversion is performed, and frequency measurement results can be obtained with predetermined digital outputs. However, if each circuit has extremely wideband characteristics, the same digital output will be obtained repeatedly at 1/τ, so a bandpass filter 2 is installed at the input of this device to determine the band to be measured. I need to put it in. In the truth table of FIG. 4, the symbol "-" means that the bit output is not used. This is because the hatched area in Figure 4a is the area where the output of the zero-cross slicer circuit 7 may exhibit both a "1" or "0" output due to receiver noise input together with the high-frequency signal. This is because if "-" is used for the first and second channels in the dead area, a large frequency measurement error will occur in the frequency division band of the dead area. Moreover, this part is also a part that does not particularly need to be used to obtain frequency measurement results. However, it is inevitable that an error in the minimum frequency division accuracy will occur due to the dead area of the third channel.

The relationship between the bit output of each channel and the frequency division band has been explained above, and the bit output of each channel is obtained according to the timing relationship shown in FIG. That is, after an input signal is detected by the detection amplifier circuit 10 and converted into a quantized output by the slicer circuit 11, each τ is calculated based on the rise time of the input signal.
+△τ, 2τ+△τ, 4τ+△τ, create delayed sampling pulses of the latch circuit 8, sample and hold the I/Q quantized output of the portion where the input signal and the delayed signal output are superimposed, respectively, When the third channel sample is completed, the digital output described above is obtained. Therefore, in the case of a three-channel configuration, an input pulse width of 4τ+Δτ is required to obtain a frequency measurement result with at least a predetermined division accuracy (LSB). Generally, in an n-channel configuration, a range of 1/τ can be measured with an accuracy of 2 ² 2 ^n-1 , but the input signal pulse width required for this is (2 ^n-1 ) τ + Δτ. Note that Δτ must be sufficiently small so that the maximum amplitude state of the I/Q video can be sufficiently sampled so as to obtain a predetermined measurement accuracy for short pulse input signals.

Conventional devices are configured as described above, so in order to improve frequency measurement accuracy, it is necessary to increase the number of channels, and as the number of channels increases, the input pulse width of the high-frequency pulse modulation signal to be measured becomes longer. It becomes necessary. Therefore, the frequency measurement result is output after 2 ^n-1 ·τ+Δτ with respect to the arrival time of the input signal. On the other hand, if the pulse width is shortened, there is a drawback that sufficient accuracy in effective frequency measurement determined by the number of channels cannot be obtained.

[Summary of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional art. A multiplier circuit is provided at the input stage of multiple channels, and the output of the I/Q phase discriminator circuit in the next stage is adjusted to the delay time τ of the delay circuit and Frequency multiplication order N
(N is an integer), and by changing it together with the carrier frequency of the pulse modulation signal, a highly accurate frequency measurement result can be obtained even if the input pulse width is short, and the frequency measurement accuracy increases depending on the input pulse width. The object is to provide an unrestricted digitized instantaneous frequency measurement device.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 6, the same reference numerals as in FIG. 1 indicate the same or corresponding parts.

30b and 30c are 2n ^-1 multiplier circuits, 4a to 4c are 2-divider circuits, 5a is a delay circuit having a delay time τ, and 6a to 6c have video amplitudes proportional to the phase difference between the two input signals. an I/Q phase discrimination circuit that outputs I/Q video outputs with a 90° phase difference; 7 discriminates the positive and negative polarities of the I/Q video outputs of the I/Q phase discrimination circuits 6a to 6c with "zero" as a reference; A zero-cross slicer circuit for quantization, 8 is a sampling pulse generation circuit 1 which will be described later.
2b is a latch circuit that temporarily stores the quantized output of the zero cross slicer circuit 7 using a sampling pulse synchronized with the arrival time of the high frequency input signal created in step 2b; This is a circuit that converts and outputs the frequency measurement result.
4 is its output terminal. In addition, 11 is a circuit that compares and quantizes the video output using the voltage applied to the reference voltage input terminal 13 as a reference, and 12b is a circuit that compares and quantizes the video output with reference to the voltage applied to the reference voltage input terminal 13. This circuit generates the signal based on a fixed standard and controls the latch circuit 8 described above. Note that the I/Q phase discrimination circuits 6a to 6c are
It operates in the same way as shown in the figure. As described above, compared to the configuration shown in FIG. 1, multiplier circuits 30b and 30c are added to the 2nd to nth channels, and the subsequent stage 2-divider circuits 4b, 4c, delay circuit 5a, and I/Q phase discrimination circuits 6b, 6c are added. The operating frequency band is twice that of bandpass filter 2...
The major differences are that the delay time of the delay circuit 5a of each channel is 2n ^-1 times larger and that the delay time of the delay circuit 5a of each channel is all constant τ.

Next, the operation of this embodiment will be explained. 6th
In the figure, a high frequency signal input to an input terminal 1 is equally distributed into n channels by an n distribution circuit 3, and each channel is divided into two distribution circuits 4a to 4c,
Delay circuit 5a and I/Q phase discrimination circuits 6a to 6c
is supplied to Here, as described above, the I and Q video outputs of the I/Q phase discrimination circuit 6a of the first channel change in proportion to the carrier frequency of the input signal, with one period of 1/τ shown in FIG. . By the way, the input signals distributed to the second channel to the nth channel are frequency multiplied by 2 times, 4 times, ...2 ^n-1 times, respectively, so the I/O of each channel is
The I and Q video outputs of the Q phase discrimination circuit each change in proportion to the carrier frequency of the input signal as follows.

I video output of the first channel I ₁ = K ₁ cos2πτ 〃 Q 〃 Q ₁ = K ₁ sin2πτ 2nd〃 I 〃
I ₂ = K ₂ cos2π・(2)・τ 〃 Q 〃
Q ₂ =K ₂ sin2π・(2)・τ 〓 〓 th n〃 I 〃
In=Kncos2π・(2 ^n-1・)・τ 〃 Q 〃
Qn=Kn sin2π・(2 ^n-1・)・τ K ₁ to Kn are constants Therefore, the period of I/Q video is 1/2τ for the second channel and 1/2 ^n-1・τ for the n-th channel. Therefore, as mentioned above in the conventional example, the delay line is
The same result can be obtained by multiplying by a factor of 2, 4,...2 ^n-1 .

The relationship between the period of the I and Q video outputs with respect to the carrier frequency of the input signal and the predetermined digital measurement output according to the processing method of each bit output is as described above. However, as shown in Fig. 7, the sampling pulses for each channel are generated approximately at τ + Δτ based on the arrival time of the input signal.
The I and Q quantized outputs at the time when the non-delayed signal 15 and the delayed signal 16 of each channel are superimposed are sampled and held to obtain the digital output described above.

Therefore, even if the pulse width of the input signal is shortened to τ + △τ, it is possible to obtain frequency measurement results with the same measurement accuracy as a long pulse, and there is a slight delay of τ + △τ with respect to the arrival time of the input signal. The frequency measurement results can be output.

In the above embodiment, the circuit shown in FIG. 2 is used as the I/Q phase discrimination circuit 6, but a mixer circuit as shown in FIG. 8 may also be used.

In addition, in FIG. 8, the same reference numerals as in FIG. 2 indicate the same or corresponding parts.

25 is a mixer, and 26 is a low pass filter. Furthermore, in the above embodiment, a multiplier circuit is provided for each channel from the second channel onwards, but since one multiplier circuit can usually provide a 2 ^n-1 multiplied output, it is shared, and a duplexer is used to connect each channel. The required multiplication output may be distributed to the

〔Effect of the invention〕

As described above, according to the present invention, a predetermined frequency measurement accuracy can be obtained regardless of the input pulse width, so that the frequency measurement accuracy can be improved even for short pulses as the number of channels increases.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional digitized instantaneous frequency measuring device, Fig. 2 is a block diagram showing an example of an I/Q phase discriminator circuit, and Fig. 3 is a diagram showing the relationship between I/Q video output and delay time with respect to input frequency. Figure 4 is a diagram showing the relationship between I/Q quantization output and processing method in the case of a 3-channel configuration, and Figure 5 is a diagram showing the case of a 3-channel configuration for a conventional device. 6 is a block diagram of a digitized instantaneous frequency measuring device according to an embodiment of the present invention. FIG. 7 is a diagram showing the time relationship of various parts in an embodiment of the present invention. FIG. 8 shows a block diagram showing another example of the I/Q phase discrimination circuit. 3...High frequency signal n distribution circuit, 30b, 30c
... Frequency multiplier circuit, 4a to 4c ... 2 distribution circuit, 5a ... Delay circuit having delay time τ, 6a
~6c...I/Q phase discrimination circuit, 7...Zero cross slicer circuit that discriminates the polarity of I/Q video output and quantizes it, 8...Latch circuit that samples and temporarily stores I/Q quantized output, 9 ...Digital output circuit, 10...A circuit that detects and amplifies an input signal, 11...A slicer circuit that detects the arrival of an input signal video based on the voltage applied to 13,
12b...Sampling pulse generation control circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 N divider that distributes the high-frequency pulse modulation signal under test into N channels, and a multiplier circuit that divides the pulse modulation signal under test of the nth channel of the divider into n(n
is an integer), the signal is divided into two, one is delayed by a delay circuit having a delay time τ, and this and the other non-delayed signal are phase-combined and detected to obtain a video amplitude proportional to the phase difference between the two signals. and an I/Q phase discrimination circuit that outputs I and Q video outputs having phases different from each other by 90 degrees;
a zero-cross slicer circuit that determines the positive and negative polarities of the video output, a plurality of latch circuits that sample and store the output of the slicer circuit in synchronization with the arrival time of the pulse modulation signal to be measured; A digital output circuit that obtains a digital frequency measurement result from the output of the latch circuit, and a timing pulse generation control circuit that generates a pulse for synchronous sampling in the latch circuit according to the arrival timing of the input signal, A digitized instantaneous frequency measuring device characterized in that the carrier frequency of a pulse modulated signal can be instantaneously measured by digital display.