JPS6134181B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-input processing device at different speeds for simultaneously processing two or more pieces of asynchronous information in a program-controlled arithmetic circuit in real time.

In program-controlled arithmetic circuits (particularly microprocessor circuits), an interrupt method is generally considered as a method for processing two or more pieces of asynchronous input information. In this method, the calculation cycle (program cycle) of the calculation circuit is synchronized with any one of the above two or more pieces of information, and for other input information, an interrupt request is calculated when that input information is received. The input information is processed by interrupts. Therefore,
Although there is an advantage that interrupt information can be processed immediately, it is complicated because it requires hardware for interrupt processing and consideration in programming to enable interrupts at arbitrary times. On the other hand, a stuffing method has been considered for multiplexing signals of different speeds, and this method is used for diversifying PCM, etc.

An object of the present invention is to easily compensate for speed differences when two or more signals having different speeds of input information are simultaneously processed in real time using a program-controlled arithmetic circuit (microprocessor, etc.). Another object of the present invention is to provide a multi-input processing device with different speeds in which a conventional stuffing method is incorporated into a program-controlled arithmetic circuit.

Next, the present invention will be explained in detail with reference to the drawings.

First, FIG. 1 shows an embodiment in which two inputs having different speeds are simultaneously processed in real time according to the present invention. Reference numerals 5 and 6 are input terminals for inputs A and B (each having different input speeds), the program storage element 2 is constituted by a ROM (read-only memory), and the arithmetic circuit 1 is constituted by a microprocessor. has been done. This ROM 2 stores an input A processing program and an input B processing program, and the execution cycle of the input A processing program is synchronized with the input speed of input A. Therefore, the calculation period of the calculation circuit 1 is synchronized with the input speed of the input A, and the information from the input A is processed without excess or deficiency, and the result is output to the output terminal 10. On the other hand, the information of input B is once buffered in buffer memory 3.
is stored in Reference numeral 4 is a buffer memory, and connections 7 and 9 are the read and write clocks for the buffer memories 3 and 4, respectively. The output of buffer memory 4 is output terminal 11
Output to. The buffer memory 3 notifies the arithmetic circuit 1 through a connection 8 of the presence or absence of information in the memory. The signal on connection 8 causes arithmetic circuit 1 to process information on input B according to the flowchart shown in FIG.

In the flowchart of FIG. 2, the processing program for input A is executed once within the execution processing time required for input A. On the other hand, the processing of input B is executed according to the signal of the connection 8 indicating the presence or absence of information in the buffer memory 3. If the information is present, the processing program of input B is executed, and if the buffer memory 3 is empty, the processing program is skipped. Let's do it. Therefore, if the speed of input A and the speed of input B completely match, the processing program for input B will be executed only once in one program cycle, but the speed of input A will be the same as that of input B.
, the processing program for input B will be executed twice during one program cycle. As shown in Figure 2, if the processing program for input B can be called twice during a program cycle, both inputs A and B can be processed in real time as long as the speed of input B is less than twice the speed of input A. is possible.

By extending this and calling the processing program for input B n times, it becomes possible to process inputs A and B in real time within a range where the speed of input B is n times the speed of input A or less.

A buffer memory 4 is placed at the output section of the arithmetic circuit 1 in order to output the processing result of the information on the input B from the output terminal 11 at the same speed as the input B or at an integral multiple thereof.
That is, a read clock is applied to the buffer memory through the connection 12, and the processing result output from the arithmetic circuit 1 at an arbitrary timing is outputted to the output terminal 11 at the cycle of the read clock.

Furthermore, FIG. 3 shows an extension of the above method to the case of multiple inputs. i.e. reference numerals 1 and 2
are an arithmetic processing circuit and a program storage element, respectively, and reference numerals 3 and 4 are buffer memories. By writing call instructions for the processing program for input A and the processing programs for inputs B, C, ..., N as many times as necessary in the main program, all information on inputs A, B, ..., N can be processed in real time. It is possible to do so.

As described above, the present invention is effective when two or more pieces of out-of-synchronization information are simultaneously processed in real time using a program-controlled arithmetic processing circuit by applying the conventional stuffing method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a flowchart showing the operation of the arithmetic processing circuit of FIG. 1, and FIG. 3 is a block diagram showing another embodiment of the present invention. 1 and 3, 1... Arithmetic processing circuit, 2... Program storage element, 3, 4... Buffer memory circuit, 5, 6... Input terminal, 7, 12... Read clock, 8... Connection, 9... Write clock ,1
0, 11...Output terminal.

Claims (1)

[Claims] 1 a first input terminal receiving a first input signal;
faster than the speed of this first input signal and N times (N
is a positive integer and has a speed equal to or lower than N>1), a buffer memory for temporarily storing the second input signal, and a buffer memory for processing the first input signal. means for detecting whether the buffer memory is empty or full N times; and means for processing the second input signal read from the buffer in response to a signal indicating that the buffer memory is full. A multi-input processing device with different speeds.