JPS6134257B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular, proposes a method for manufacturing a semiconductor device having a multilayer wiring structure.

In semiconductor devices such as semiconductor integrated circuits (ICs), wiring formed on a semiconductor substrate has a multilayer wiring structure of two or more layers in order to improve the degree of integration.

As a manufacturing method for realizing such a multilayer wiring structure, the steps shown in FIGS. 1 to 4 have conventionally been generally adopted.

That is, first, as shown in FIG. 1, an aluminum layer with a thickness of about 1 [μm] is selectively deposited on an insulating film 12 formed on the surface of a semiconductor substrate 11, and a first layer having a predetermined pattern is formed. A layer (lower layer) wiring layer 13 is formed. The aluminum layer is deposited on the entire surface of the insulating film 12 by vapor deposition or the like, and is formed into a predetermined wiring pattern by applying photolithography technology.

As shown in FIG. 2, the first wiring layer 13 and the insulation film 12 are then covered to a thickness of 1 μm.
m] of interlayer insulating layer 14 is formed. The interlayer insulating layer 14 is made of phosphorus silicate glass (PSG), for example.
It is formed by a gas phase reaction with phosphine (PH ₃ ), monosilane (SiH ₄ ) and oxygen (O ₂ ). According to such a gas phase reaction method, abnormal growth of the phosphorus silicate glass layer 14 occurs at the shoulder portion of the first wiring layer 13, resulting in a thick portion 14' and a thin portion 14''.

Next, as shown in FIG. 3, the interlayer insulating layer 14 on a predetermined portion of the first wiring layer 13 is removed to form an interlayer connection hole (through hole) 15. A normal photolithography technique is applied to selectively remove the interlayer connection layer 14. The opening edge of the interlayer contact hole 15 formed by such selective removal of the interlayer insulating layer 14 also has a steep slope.

Next, as shown in FIG. 4, the interlayer connection hole 1
First layer wiring and interlayer insulating layer 1 exposed by 5
A second (upper) wiring layer 16 having a predetermined pattern is formed by selectively depositing an aluminum layer having a thickness of about 1 [μm] over the wiring layer 4. The aluminum layer is also deposited by vapor deposition or the like, and then photolithography is applied to form it into a predetermined pattern.

In a multilayer wiring structure formed by such a conventional general method, the first wiring layer 13
The thick part of the interlayer insulating layer 14 that occurs at the shoulder part of
Due to the thin and steep parts, the second wiring layer 16 also has thick parts and thin parts corresponding to the thin parts, and the second wiring layer 16 is likely to break or cross. In the wiring part, the first wiring layer 13 and the second
Short circuits with the wiring layer 16 are likely to occur, which is a factor in lowering the manufacturing yield and reliability of the semiconductor device.

In order to eliminate such defects, for example, after forming the first wiring layer, a liquid insulator is applied to both sides of the first wiring layer and cured by heating to coat the side surfaces of the first wiring layer. It has been proposed to smooth the surface and then apply an interlayer insulating layer, but such a method increases the number of manufacturing steps.

In manufacturing a semiconductor device having a multilayer wiring structure, the present invention forms a gentle slope in a lower wiring layer and an interlayer insulating layer without causing a significant increase in the number of manufacturing steps, thereby preventing disconnections in upper wiring layers and gaps between wiring layers. The object is to provide a manufacturing method that does not cause short circuits.

Therefore, according to the present invention, the first
A wiring layer is formed of aluminum or an aluminum alloy, an insulating layer is formed to cover the first wiring layer, an opening is formed in the insulating layer at a portion where interlayer connection is to be made, and then an insulating layer is formed on the first wiring layer. By irradiating energy beams to melt the insulating layer, the side edges of the first wiring layer covered with the insulating layer are melted, and the surface of the first wiring layer and the first wiring layer is melted. A method of manufacturing a semiconductor device is provided, in which a second wiring layer is formed on the insulating layer, which has been flattened with a gentle slope, and is interlayer connected to the first wiring layer through the opening.

The present invention will be explained in detail below using examples.

5 to 11 are process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

According to the present invention, first, as shown in _FIG . layer 10
3 is deposited.

Although not shown in the drawings, the semiconductor substrate 101 has an impurity-introduced region that constitutes an active element such as a transistor and/or a passive element such as a resistor. The insulating film 102 can be formed by thermally oxidizing the surface of the semiconductor substrate 101 or by a vapor deposition (CVD) method. Further, the aluminum layer 103 is formed by a vapor deposition method or the like.

Next, as shown in FIG. 6, the aluminum layer 103 is selectively removed to form desired wiring layers 104A and 104B. Ordinary photolithography techniques can be applied to selectively remove the aluminum layer 103.

Next, as shown in FIG. 7, the wiring layer 1
04A, 104B and exposed insulation film 10
An interlayer insulating layer 105 with a thickness of about 1 [μm] covers 2.
is deposited. The interlayer insulating layer 105 is made of phosphorus silicate glass (PSG), and is formed by a gas phase reaction with phosphine (PH ₃ ), monosilane (SiH ₄ ), and oxygen (O ₂ ). According to such a gas phase reaction, abnormal growth of the phosphorus silicate glass layer 105 occurs in the shoulder portions of the wiring layers 104A and 104B, resulting in thick portions and thin portions.

Next, as shown in FIG. 8, a wiring layer 104 is formed.
The interlayer insulating layer 105 is selectively removed on a predetermined portion of A, and an interlayer connection hole (through hole) 106 is formed. A normal photolithography technique is applied to selectively remove the interlayer insulating layer 105. The opening edge of the interlayer contact hole 106 formed by selectively removing the interlayer insulating layer 105 also has a steep slope.

According to the present invention, laser irradiation is then applied to at least the wiring layers 104A and 104B, and the wiring layers 104A and 104B and the interlayer insulating layer 105 covering the wiring layers are once melted, as shown in FIG. At the same time, the shoulders of the wiring layers 104A and 104B are rounded or gently sloped, and the thin part that had appeared in the interlayer insulating layer 105 is eliminated, and the opening edge of the interlayer connection hole 106 is also sloped gently. considered as something.

Here, a carbon dioxide (CO ₂ ) gas laser (wavelength: 10.6 [μm]) is used as the heating laser. The laser beam has a pulse width of 1.0 [μ
The semiconductor substrate to be processed is irradiated vertically or obliquely as pulsed light with an energy density of 1 to 3 J/cm ² and a spot diameter of 5 to 20 [mm]. During irradiation with such laser light, the irradiation position of the laser light is fixed and the semiconductor substrate to be processed is moved in the X direction and the Y direction. In addition, if a mask with an appropriate rectangular aperture is placed in the middle of the laser beam path,
It becomes possible to irradiate each semiconductor element (chip) on a semiconductor substrate. A carbon dioxide laser has almost no heating effect even when directly irradiated onto aluminum, but when covered with phosphorus silicate glass, the aluminum is melted by the heat absorbed by the phosphorus silicate glass.

According to the present invention, as shown in FIG.
An aluminum layer 107 of about [μm] is deposited. At this time, there is a steep step on the interlayer insulating layer 105.
Since there are no irregularities, the aluminum layer 107 is deposited to a substantially uniform thickness.

Thereafter, photolithography is applied to selectively remove the aluminum layer 107 to form an upper wiring layer 108 as shown in FIG. The upper wiring layer 108 is the interlayer insulating layer 1
Since there are no steep steps, irregularities, or thin parts in 05, there is no thin part and there is no risk of short circuiting with the underlying wiring.

As described above, according to the present invention, after forming the lower wiring layer and the interlayer insulating layer, at least the lower wiring layer portion is irradiated with a laser beam to temporarily melt the lower wiring layer and the interlayer insulation layer covering the lower wiring layer. By doing so, the slope and unevenness of the surface of the interlayer insulating layer are smoothed. After that, an upper wiring layer is formed. Therefore, disconnection of the upper wiring layer or short circuit between the upper wiring layer and the lower wiring layer does not occur, and the manufacturing yield and reliability of the semiconductor device can be improved.

In the above embodiments, a laser beam was used as the heating energy beam, but it goes without saying that an electron beam may also be used.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views showing manufacturing steps of a conventional semiconductor device manufacturing method, and FIGS. 5 to 11 are process cross-sectional views showing an embodiment of the present invention. In the drawings, 11,101...semiconductor substrate,
12,102...Insulating film, 13,104A,1
04B...First layer (lower layer) wiring layer, 14,105
. . . interlayer insulating layer, 16, 108 . . . second layer (upper layer) wiring layer.

Claims (1)

[Claims] 1. Form a first wiring layer of aluminum or aluminum alloy on a semiconductor substrate, then form an insulating layer covering the first wiring layer, provide an opening in the insulating layer at a portion where interlayer connection is to be made, and then By irradiating an energy beam onto the first wiring layer and melting the insulating layer, the side end of the first wiring layer covered with the insulating layer is melted and the first wiring layer and the first wiring layer are melted. The surface of the first wiring layer is made to have a gentle slope, and then a second wiring layer is formed on the flattened insulating layer.
1. A method of manufacturing a semiconductor device, comprising: forming a wiring layer, and making an interlayer connection to a first wiring layer through the opening.