JPS6135156B2 - - Google Patents
Info
- Publication number
- JPS6135156B2 JPS6135156B2 JP20782181A JP20782181A JPS6135156B2 JP S6135156 B2 JPS6135156 B2 JP S6135156B2 JP 20782181 A JP20782181 A JP 20782181A JP 20782181 A JP20782181 A JP 20782181A JP S6135156 B2 JPS6135156 B2 JP S6135156B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- circuit
- conductive paste
- printed board
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はセラミツクプリント板の製造方法に
関し、特に回路導体となる導電ペーストの選択
に関し提示するセラミツクプリント板の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a ceramic printed board, and more particularly to a method for manufacturing a ceramic printed board that concerns the selection of a conductive paste to serve as a circuit conductor.
(2) 従来技術と問題点
例えばアルミナ系セラミツクは電気絶縁性、
耐熱性、熱伝導性に秀れ、機械的強度も高いこ
とから近時の高密度の三次元導体回路を形成す
るプリント基板材料として賞用されている。か
かるセラミツク基材から所望とする三次元導体
回路生成の要部手段とその問題点を図に従がい
説明する。(2) Conventional technology and problems For example, alumina ceramic has electrical insulation properties,
Because it has excellent heat resistance, thermal conductivity, and high mechanical strength, it is being used as a printed circuit board material for forming high-density three-dimensional conductor circuits. The main means for producing a desired three-dimensional conductor circuit from such a ceramic base material and the problems involved will be explained with reference to the drawings.
第1図の製造工程線図において、Aは焼成前
のセラミツク基板いわゆるグリーンシートと呼
ばれる基板に対して、孔あけをなす工程であ
る。即ち、グリーンシートを多数積層したとき
上下層間の回路接続をなすためのスルーホール
(あるいはバイヤホール)あけの孔明工程であ
る。 In the manufacturing process diagram of FIG. 1, A is the step of drilling holes in a ceramic substrate, so-called green sheet, before firing. That is, this is a drilling process for making through holes (or via holes) for making circuit connections between upper and lower layers when a large number of green sheets are stacked.
Bは前記スルーホールに導電性のよい例えば
金等の貴金属粉末と、無機バインダ、及び若干
の溶剤からなるペーストを充填する工程であ
る。 B is a step of filling the through hole with a paste consisting of powder of a noble metal such as gold having good conductivity, an inorganic binder, and some solvent.
Cは前記スルーホール導通処理に続いてグリ
ーンシートの表面において、例えばステンシル
クスクリーン印刷手法により、前記組成と同一
の導電性ペーストを所定の回路パターンに印刷
し回路(第2図の4参照)を形成する工程であ
る。 C is a circuit (see 4 in Fig. 2) by printing a conductive paste having the same composition as the above in a predetermined circuit pattern on the surface of the green sheet following the through-hole conduction process, for example, by using a stencil screen printing method. This is the process of forming.
Dは前記スルーホール接続並びに回路パター
ン形成ずみのグリーンシートを幾層にも積み重
ねて立体化回路が組立られる工程である。 D is a step in which a three-dimensional circuit is assembled by stacking the green sheets on which the through-hole connections and circuit patterns have been formed in many layers.
そしてEは前記のD工程で積層完了せるグリ
ーンシート体を例えば850℃で10分間焼成し多
層セラミツク板を形成する工程である。 Step E is a step in which the green sheets, which have been laminated in step D, are fired at, for example, 850.degree. C. for 10 minutes to form a multilayer ceramic board.
ところがこの様な製造工程により完成した多
層セラミツク板1にあつては、第2図断面図に
例示する上下に貫通のスルーホール3部分で該
スルーホール内接続用充填ペーストが外方にふ
くれ2を生じ製品としての使用には不適切であ
る。例えば図示にないが、LSI等の素子を基板
表面(あるいは裏面)に実装するさい正規の実
装が出来ない等の支障を来たす。 However, in the multilayer ceramic board 1 completed by such a manufacturing process, the filling paste for connection in the through-holes bulges 2 outward at the through-holes 3 that penetrate upward and downward, as illustrated in the cross-sectional view of FIG. Unsuitable for use as a raw product. For example, although not shown in the drawings, when mounting an element such as an LSI on the front surface (or back surface) of a substrate, it may cause problems such as not being able to perform proper mounting.
このため、前記スルーホール充填の導体ペー
ストに対し、セラミツク焼成時における温度特
性につき調査したところ第3図に実線aで示さ
れる温度(横軸tであらわす)対寸法変化特性
(縦軸、0から上方は寸法増加の領域又0から
下方は寸法減少の領域を示す)を有していた。 For this reason, we investigated the temperature characteristics of the through-hole filling conductor paste during ceramic firing, and the temperature (represented by the horizontal axis t) versus dimensional change characteristics (vertical axis, from 0 to The upper part shows a region of increasing size, and the lower part from 0 shows a region of decreasing size).
すなわち、図から明らかなように、スルーホ
ール内導電ペーストは、温度t1(約800℃)ま
では収縮域にあるも、t1から高い温度では膨脹
しかも急激な勾配で寸法が増加する。これは多
分、ペースト組成中の無機バインダが分解し多
量のガスを発生するためであり、これが前記ふ
くれの主因であることは明らかである。 That is, as is clear from the figure, the conductive paste in the through-hole is in a shrinkage range up to temperature t 1 (approximately 800° C.), but expands and increases in size at a steep gradient at temperatures higher than t 1 . This is probably because the inorganic binder in the paste composition decomposes and generates a large amount of gas, which is clearly the main cause of the blistering.
(3) 発明の目的
本発明は立体回路形式の積層セラミツク板焼
成時発生するスルーホール接続部のふくれを解
消し前記第1図製造プロセスによる安定なかつ
製品歩留りのよい回路形成方法を実現すること
である。(3) Purpose of the Invention The present invention eliminates the bulging of through-hole connections that occurs when firing a three-dimensional circuit type laminated ceramic board, and realizes a circuit forming method that is stable and has a high product yield using the manufacturing process shown in FIG. be.
(4) 発明の構成
回路パターンが生成された未焼成セラミツク
基板を複数枚積層しかつこれを焼成してするセ
ラミツクプリント板の製造において、未焼成セ
ラミツク基板に形成された層間接続用孔内にガ
ラスフリツトを含む導電ペースト充填をなし、
次いで前記未焼成セラミツク基板の表面にガラ
スフリツトを含まない導電ペーストにより回路
パターンを印刷し、然るのち前記未焼成セラミ
ツク基板を積層して焼成してなすセラミツクプ
リント板の製造方法にある。(4) Structure of the invention In manufacturing a ceramic printed board by laminating and firing a plurality of unfired ceramic substrates on which circuit patterns have been generated, glass frit is inserted into interlayer connection holes formed in the unfired ceramic substrates. No conductive paste filling, including
Next, a circuit pattern is printed on the surface of the unfired ceramic substrate using a conductive paste containing no glass frit, and then the unfired ceramic substrates are laminated and fired.
(5) 発明の実施例
前記構成のガラスフリツトは粒形1もしくは
1ミクロン以下の低触点ガラス微粉体を指摘す
るもので金属とガラスとの気密接合基材として
賞用される。(5) Embodiments of the Invention The glass frit having the above structure is a low contact point glass fine powder with a particle size of 1 or 1 micron or less, and is used as a base material for airtight bonding of metal and glass.
これを第1図製造工程のB工程で充填する導
電ペースト中に添加しかつ混練して使用する。
即ち、スルーホールあるいはバイヤホールのシ
ール孔あけ部に充填する層間回路接続に用いる
導電ペーストはガラスフリツト添加、添加量は
重量比にして約1%程度のものを使用する。 This is added to the conductive paste to be filled in step B of the manufacturing process in FIG. 1, and used by kneading.
That is, the electrically conductive paste used for interlayer circuit connection, which is filled in the sealing hole portion of the through hole or via hole, contains glass frit in an amount of approximately 1% by weight.
しかし、第1図製造工程のC工程において、
各グリーンシート面にパターン印刷して回路パ
ターン形成の導電ペーストはガラスフリツト添
加のないガラスフリツトレス導電ペーストを用
いる。 However, in step C of the manufacturing process in Figure 1,
A glass fritless conductive paste without added glass frit is used as the conductive paste for forming a circuit pattern by printing patterns on the surface of each green sheet.
因に本発明に係る前記スルーホール接続用ガ
ラスフリツト添加の導電ペーストに対するセラ
ミツク焼成温度に対する第3図の寸法的挙動を
示すと、一点鎖線b特性で示される。 Incidentally, the dimensional behavior of the glass frit-added conductive paste for through-hole connection according to the present invention as shown in FIG. 3 with respect to the ceramic firing temperature is shown by the dot-dashed line b characteristic.
前記ガラスフリツト添加にさいし添加前導体
ペーストは、例えばモリブデン・タングステン
組成のペーストとか銀パラジウム組成のペース
トを使用することが出来る。もちろん対象ペー
ストによりフリツト添加は最適とする量があ
り、これが多いとスルーホールの電気的接続抵
抗が増大するため注意を要する。 When adding the glass frit, for example, a paste having a molybdenum-tungsten composition or a paste having a silver-palladium composition can be used as the pre-addition conductor paste. Of course, there is an optimal amount of frit to be added depending on the target paste, and care must be taken because if this amount is too large, the electrical connection resistance of the through holes will increase.
第1図のB並びにC工程で形成された導体回
路形成のグリーンシート体を積層し、従来同様
のセラミツク焼成温度t2=850〔℃〕程度で焼
結することにすれば(D工程)安定なセラミツ
ク基板を得ることが出来る。 If the conductor circuit-forming green sheet bodies formed in steps B and C in Figure 1 are stacked and sintered at the same ceramic firing temperature t 2 = 850 [°C] as in the past (step D), it will be stable. A ceramic substrate of high quality can be obtained.
(6) 発明の効果
以上説明の本発明のセラミツクプリント板の
製造方法によれば、従来あつた様な積層セラミ
ツクプリント板のホール接続部3にたいするふ
くれ(第2図の5参照)等生じない安定とする
三次元回路を具えるプリント板が形成される。
併せて該プリント板の製造能力も向上するため
その実用価値は大きい。(6) Effects of the Invention According to the method for manufacturing a ceramic printed board of the present invention as described above, it is stable and does not cause blisters (see 5 in Fig. 2) in the hole connecting portions 3 of a laminated ceramic printed board as in the conventional case. A printed board with a three-dimensional circuit is formed.
At the same time, the manufacturing capacity of the printed board is improved, so its practical value is great.
第1図はセラミツクプリント板の製造工程図、
第2図は本発明の対象セラミツクプリント板の断
面図、第3図はセラミツク焼成温度tに対するス
ルーホール導体部の寸法変化の特性を示す。
図中、1はセラミツクプリント板、2は1の表
(裏)面におけるスルーホール部3のふくれ及び
4は導体ペーストによる印刷回路導体である。
Figure 1 is a diagram of the manufacturing process for ceramic printed boards.
FIG. 2 is a sectional view of a ceramic printed board to which the present invention is applied, and FIG. 3 shows the characteristics of dimensional changes of through-hole conductor portions with respect to ceramic firing temperature t. In the figure, 1 is a ceramic printed board, 2 is a bulge in a through-hole portion 3 on the front (back) surface of 1, and 4 is a printed circuit conductor made of conductive paste.
Claims (1)
基板を複数枚積層しかつこれを焼成するセラミツ
クプリント板の製造において、未焼成セラミツク
基板に形成された層間接続用孔内にガラスフリツ
トを含む導電ペーストを充填し、次いで前記未焼
成セラミツク基板の表面にガラスフリツトを含ま
ない導電ペーストにより回路パターンを印刷し、
然るのち前記未焼成セラミツク基板を積層して焼
成する工程を有することを特徴とするセラミツク
プリント板の製造方法。1. In manufacturing a ceramic printed board by laminating and firing a plurality of unfired ceramic substrates on which circuit patterns have been generated, conductive paste containing glass frit is filled into interlayer connection holes formed in the unfired ceramic substrate. Next, a circuit pattern is printed on the surface of the unfired ceramic substrate using a conductive paste that does not contain glass frit,
A method for manufacturing a ceramic printed board, comprising the step of laminating and firing the unfired ceramic substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20782181A JPS58110480A (en) | 1981-12-22 | 1981-12-22 | Manufacture of ceramic print board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20782181A JPS58110480A (en) | 1981-12-22 | 1981-12-22 | Manufacture of ceramic print board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58110480A JPS58110480A (en) | 1983-07-01 |
| JPS6135156B2 true JPS6135156B2 (en) | 1986-08-11 |
Family
ID=16546060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20782181A Granted JPS58110480A (en) | 1981-12-22 | 1981-12-22 | Manufacture of ceramic print board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58110480A (en) |
-
1981
- 1981-12-22 JP JP20782181A patent/JPS58110480A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58110480A (en) | 1983-07-01 |
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