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JPS6135628B2 - - Google Patents
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JPS6135628B2 - - Google Patents

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Publication number
JPS6135628B2
JPS6135628B2 JP53137481A JP13748178A JPS6135628B2 JP S6135628 B2 JPS6135628 B2 JP S6135628B2 JP 53137481 A JP53137481 A JP 53137481A JP 13748178 A JP13748178 A JP 13748178A JP S6135628 B2 JPS6135628 B2 JP S6135628B2
Authority
JP
Japan
Prior art keywords
transistor
resistor
base
emitter
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53137481A
Other languages
Japanese (ja)
Other versions
JPS5564684A (en
Inventor
Fumihiko Sato
Yoji Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13748178A priority Critical patent/JPS5564684A/en
Publication of JPS5564684A publication Critical patent/JPS5564684A/en
Publication of JPS6135628B2 publication Critical patent/JPS6135628B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Description

【発明の詳細な説明】 本発明は、集積回路装置に関するものである。[Detailed description of the invention] The present invention relates to an integrated circuit device.

近時、集積回路の高速化、低電力化が要求され
ており、それに伴いより小さな論理振幅が使用さ
れるようになつてきている。しかし論理振幅が小
さい程回路動作が不安定になるという傾向が存在
している。特に抵抗と非線型素子であるダイオー
ド等が並列接続された負荷による電位降下を出力
信号振幅として用い、かつ基準電圧との電位差を
次段の駆動電圧として用いる回路では、出力信号
振幅と基準電圧の温度変動の違いにより、温度が
変化した場合駆動電圧が小さくなり回路動作が不
安定になるという可能性がある。従つて温度が変
化しても常に信号振幅の中央に基準電圧が設定さ
れるようにして回路の安定化を図る必要がある。
Recently, there has been a demand for higher speed and lower power consumption of integrated circuits, and as a result, smaller logic amplitudes are being used. However, there is a tendency that the smaller the logic amplitude, the more unstable the circuit operation becomes. In particular, in a circuit that uses the potential drop due to a load in which a resistor and a nonlinear element such as a diode are connected in parallel as the output signal amplitude, and uses the potential difference with the reference voltage as the next stage drive voltage, the output signal amplitude and the reference voltage are Due to differences in temperature fluctuations, there is a possibility that when the temperature changes, the drive voltage decreases and circuit operation becomes unstable. Therefore, it is necessary to stabilize the circuit by always setting the reference voltage at the center of the signal amplitude even if the temperature changes.

本発明の目的はメモリセルの読出し等において
温度変化による基準電圧の中央値からのずれを防
ぎ、回路動作の安定な集積回路装置を提供するこ
とにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device that prevents deviation of a reference voltage from a median value due to temperature changes during reading of memory cells, etc., and provides stable circuit operation.

本発明集積回路装置は、ベースとコレクタとが
交互に接続された第1、第2のトランジスタとそ
れぞれのコレクタと信号線との間に接続された非
線型素子を含む第1、第2の負荷素子とからなる
フリツプフロツプと、前記第1、第2のトランジ
スタのエミツタにそれぞれのエミツタが接続さ
れ、コレクタがそれぞれ出力端子に接続されると
ともの負荷抵抗を介して、第1の電源に接続され
た第3、第4のトランジスタを含む電位検出手段
と、エミツタが第2の電源に接続されベースが第
1の抵抗を介して第2の電源に接続され、コレク
タが第2の抵抗を介して第1の電源に接続された
第5のトランジスタとエミツタが第3の抵抗を介
して第1のトランジスタのベースに接続され、ベ
ースが第1のトランジスタのコレクタに接続さ
れ、コレクタが第1の電源に接続された第6のト
ランジスタとからなる電源回路と、エミツタが第
4の抵抗を介して第2の電源に接続されベースが
前記第6のトランジスタのエミツタに接続され、
コレクタが第5の抵抗を介して第1の電源に接続
された第7のトランジスタを含み、前記第3、第
4のトランジスタのベースに基準電位を供給する
基準電位発生回路とを有し、前記基準電位の温度
変動と前記第1、第2の負荷による電位降下の温
度変動とが所定比になるように、前記非線型素子
の順方向電圧の温度係数と前記第5のトランジス
タのベースエミツタ間電圧の温度係数とがほぼ等
しく設定され、かつ前記第1、第4の抵抗の抵抗
値の積と前記第3、第5の抵抗の抵抗値の積との
比が決定されていることを特徴とする。
The integrated circuit device of the present invention has first and second loads including first and second transistors whose bases and collectors are alternately connected and a nonlinear element connected between the respective collectors and a signal line. a flip-flop consisting of a flip-flop element, the emitters of which are connected to the emitters of the first and second transistors, the collectors of which are connected to the respective output terminals, and the flip-flop is connected to a first power source via a load resistor; potential detection means including third and fourth transistors, an emitter connected to a second power source, a base connected to the second power source via a first resistor, and a collector connected to the second power source via the second resistor. a fifth transistor connected to the first power supply and an emitter connected to the base of the first transistor via a third resistor; the base is connected to the collector of the first transistor; and the collector is connected to the first power supply. a power supply circuit comprising a sixth transistor connected to the sixth transistor; an emitter connected to the second power supply via a fourth resistor and a base connected to the emitter of the sixth transistor;
a reference potential generation circuit including a seventh transistor whose collector is connected to the first power supply via a fifth resistor and supplies a reference potential to the bases of the third and fourth transistors; The temperature coefficient of the forward voltage of the nonlinear element and the base-emitter voltage of the fifth transistor are adjusted such that the temperature fluctuation of the reference potential and the temperature fluctuation of the potential drop due to the first and second loads are at a predetermined ratio. temperature coefficients are set to be approximately equal, and a ratio of the product of the resistance values of the first and fourth resistors to the product of the resistance values of the third and fifth resistors is determined. do.

第1図に本発明の一実施例によるメモリの読み
出し回路を示す。トランジスタQ1,Q2はフリツ
プフロツプを構成しその負荷として抵抗R1とダ
イオードD1及び抵抗R2とダイオードD2をそれぞ
れ並列接続したものを使用している。メモリーセ
ルの記憶情報を検出するための基準電圧発生回路
はトランジスタQ3〜Q10、抵抗R3〜R8により構成
されている。抵抗R11,R12は出力の負荷抵抗であ
る。回路14はメモリーセルの記憶情報読み出し
時トランジスタQ9を導通させトランジスタQ7
よびQ8を非導通とする信号を基準電圧発生回路
に送るための書き込み入力バツフア回路であり、
トランジスタQ11,Q12及び抵抗R9,R10,R13
構成された電源回路は基準電圧発生回路のトラン
ジスタQ10、抵抗R8を含む電流源回路を駆動す
る。
FIG. 1 shows a memory read circuit according to an embodiment of the present invention. Transistors Q 1 and Q 2 constitute a flip-flop, and use resistor R 1 and diode D 1 and resistor R 2 and diode D 2 connected in parallel as loads. A reference voltage generation circuit for detecting information stored in a memory cell is composed of transistors Q 3 to Q 10 and resistors R 3 to R 8 . Resistors R 11 and R 12 are output load resistances. The circuit 14 is a write input buffer circuit for sending a signal to the reference voltage generation circuit to make transistor Q 9 conductive and transistors Q 7 and Q 8 non-conductive when reading information stored in the memory cell.
A power supply circuit composed of transistors Q 11 , Q 12 and resistors R 9 , R 10 , R 13 drives a current source circuit including transistor Q 10 and resistor R 8 of the reference voltage generation circuit.

メモリセルの記憶読み出しはアドレス線10に
よりメモリーセルが選ばれている時、フリツプフ
ロツプを形成するトランジスタQ1又はQ2のいず
れかが導通しているかを、トランジスタQ3又は
Q4のベース電位とトランジスタQ1又はQ2のベー
ス電位とを比較することにより検出し、検出した
信号は負荷抵抗R11,R12により出力として得られ
る。すなわちトランジスタQ1が導通し、トラン
ジスタQ2が非導通の場合、定電流源Ibの電流
は、トランジスタQ1から流れ、定電流源Iaの電
流はトランジスタQ4から流れる。従つてトラン
ジスタQ3は非導通、トランジスタQ4は導通とい
う状態となり、この電流が負荷抵抗R12に流れ出
力電圧として検出される。この時抵抗R1とダイ
オードD1の合成抵抗による電位降下が大きい程
メモリーセルの動作は安定し、かつ基準電位とな
るトランジスタQ3及びQ4のベース電位の可変範
囲は広くなりノイズマージンが大きくなる。しか
し温度変化によりダイオードD1の接合電圧が小
さくなつた場合合成抵抗による電位降下が小さく
なる。この時基準電位が温度変化により影響を受
けない場合、基準電位が合成抵抗の振幅の中央値
からずれるため誤動作の原因となる可能性が生じ
て来る。本発明はこのように温度変化により電位
が変化する信号に対し常に信号電圧の中央値に基
準電圧を設定するため、基準電圧発生回路の電流
源回路を駆動する電源回路に適切な温度特性を持
たせた事を特徴としている。電源回路内のトラン
ジスタQ12のベースエミツタ間電圧VBE(Q12)と
電流源回路のトランジスタQ10のベースエミツタ
間電圧VBE(Q10)を等しくした時、抵抗R8の両
端の電圧は抵抗R9の両端の電圧に等しくなる。
又抵抗R9の両端の電圧V(R9)はトランジスタ
Q12のベースエミツタ間電圧VBE(Q12)及び抵抗
R9,R10により次式のような関係で表わされる。
To read the memory of a memory cell, when the memory cell is selected by the address line 10, it is determined whether transistor Q 1 or Q 2 forming a flip-flop is conducting .
It is detected by comparing the base potential of Q4 and the base potential of transistor Q1 or Q2 , and the detected signal is obtained as an output by load resistors R11 and R12 . That is, when transistor Q 1 is conductive and transistor Q 2 is non-conductive, the current of constant current source Ib flows from transistor Q 1 and the current of constant current source Ia flows from transistor Q 4 . Therefore, transistor Q 3 becomes non-conductive and transistor Q 4 becomes conductive, and this current flows through load resistor R 12 and is detected as an output voltage. At this time, the larger the potential drop due to the combined resistance of resistor R 1 and diode D 1 , the more stable the operation of the memory cell becomes, and the wider the variable range of the base potential of transistors Q 3 and Q 4 , which serve as the reference potential, and the larger the noise margin. Become. However, when the junction voltage of the diode D1 becomes smaller due to a temperature change, the potential drop due to the combined resistance becomes smaller. If the reference potential is not affected by temperature changes at this time, there is a possibility that the reference potential will deviate from the median value of the amplitude of the combined resistance, causing malfunction. The present invention always sets the reference voltage to the median value of the signal voltage for signals whose potential changes due to temperature changes, so the power supply circuit that drives the current source circuit of the reference voltage generation circuit has appropriate temperature characteristics. It is characterized by having When the base-emitter voltage V BE (Q 12 ) of transistor Q 12 in the power supply circuit and the base-emitter voltage V BE (Q 10 ) of transistor Q 10 in the current source circuit are made equal, the voltage across resistor R 8 is equal to resistor R It will be equal to the voltage across 9 .
Also, the voltage V (R 9 ) across the resistor R 9 is
Base-emitter voltage V BE (Q 12 ) and resistance of Q 12
The relationship between R 9 and R 10 is expressed by the following equation.

V(R9)=R9・VBE(Q12)/R10 (1) 従つてV(R9)の温度変動はVBE(Q12)の温度
変動に抵抗比(R9/R10)をかけた値が得られ
る。又、基準電圧を決定する抵抗R7の両端の電
圧V(R7)は V(R7)=R7・V(R8)/R8 (2) となる。従つて(1),(2)式により次式が得られ
る。
V (R 9 ) = R 9・V BE (Q 12 )/R 10 (1) Therefore, the temperature fluctuation of V (R 9 ) is the resistance ratio (R 9 /R 10 ) to the temperature fluctuation of V BE (Q 12 ). ) is obtained. Further, the voltage V(R 7 ) across the resistor R 7 that determines the reference voltage is V(R 7 )=R 7 ·V(R 8 )/R 8 (2). Therefore, the following equation can be obtained from equations (1) and (2).

V(R7) =R7・V(R8)/R8 =R7・V(R9/R8 =R7・R9・VBE(Q12)/R8・R10 (3) 抵抗の温度変動率はすべて等しいと考えられる
ので基準電圧の温度変動はトランジスタQ12のベ
ースエミツタ間電圧の温度変動ΔVBE(Q12)と
抵抗比(R7・R9/R8・R10)により決まる。
V (R 7 ) = R 7 · V (R 8 ) / R 8 = R 7 · V (R 9 / R 8 = R 7 · R 9 · V BE (Q 12 ) / R 8 · R 10 (3) Since the temperature fluctuation rate of all resistors is considered to be equal, the temperature fluctuation of the reference voltage is the temperature fluctuation of the base-emitter voltage of transistor Q12 ΔV BE (Q 12 ) and the resistance ratio (R 7 · R 9 /R 8 · R 10 ) Determined by

従つて検出される側の信号の温度変動、すなわ
ちダイオードD1又はD2の接合電圧の温度変動Δ
D1,ΔVD2がトランジスタQ12のベースエミツ
タ間電圧の温度変動ΔVBE(Q12)にほぼ等しい
と考えられる時、基準電圧側の温度変動は、(3)式
に示された抵抗比(R7・R9/R8・R10)を1/2にす
ることにより基準電圧を温度変化に影響されずに
常に検出信号の中央値に設定する事が可能とな
る。
Therefore, the temperature fluctuation of the signal on the side to be detected, that is, the temperature fluctuation of the junction voltage of diode D 1 or D 2 Δ
When V D1 and ΔV D2 are considered to be approximately equal to the temperature variation ΔV BE (Q 12 ) of the base-emitter voltage of transistor Q 12 , the temperature variation on the reference voltage side is calculated by the resistance ratio (R By reducing 7・R 9 /R 8・R 10 ) to 1/2, it is possible to always set the reference voltage to the median value of the detection signal without being affected by temperature changes.

このように本発明はメモリセル等の読み出しを
温度変化に影響されず安定に行なう事に非常に有
効である。又本発明はメモリの読み出し以外の回
路にも広く適用しうるものである。
As described above, the present invention is very effective in stably reading data from memory cells and the like without being affected by temperature changes. Furthermore, the present invention can be widely applied to circuits other than memory read circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を半導体メモリの読
み出し回路の場合について示す回路図である。 図において、Q1〜Q12……トランジスタ、R1
R13……抵抗、D1,D2……シヨツトキダイオー
ド、Ia,Ib……定電流源、VEE……定電圧源を示
す。
FIG. 1 is a circuit diagram showing an embodiment of the present invention in the case of a read circuit for a semiconductor memory. In the figure, Q 1 to Q 12 ... transistors, R 1 to
R 13 ...resistor, D 1 , D 2 ... shotgun diode, Ia, Ib ... constant current source, V EE ... constant voltage source.

Claims (1)

【特許請求の範囲】[Claims] 1 ベースとコレクタとが交互に接続された第
1、第2のトランジスタと、それぞれのコレクタ
と信号線との間に接続された非線型素子を含む第
1、第2の負荷素子とからなるフリツプフロツプ
と、前記第1、第2のトランジスタのエミツタに
それぞれのエミツタが接続され、コレクタがそれ
ぞれ出力端子に接続されるとともに負荷抵抗を介
して、第1の電源に接続された第3、第4のトラ
ンジスタを含む電位検出手段と、エミツタが第2
の電源に接続されベースが第1の抵抗を介して第
2の電源に接続され、コレクタが第2の抵抗を介
して第1の電源に接続された第5のトランジスタ
と、エミツタが第3の抵抗を介して第5のトラン
ジスタのベースに接続され、ベースが第5のトラ
ンジスタのコレクタに接続され、コレクタが第1
の電源に接続された第6のトランジスタとからな
る電源回路と、エミツタが第4の抵抗を介して第
2の電源に接続され、ベースが前記第6のトラン
ジスタのエミツタに接続され、コレクタが第5の
抵抗を介して第1の電源に接続された第7のトラ
ンジスタを含み、前記第3、第4のトランジスタ
のベースに基準電位を供給する基準電位発生回路
とを有し、前記基準電位の温度変動と前記第1、
第2の負荷による電位降下の温度変動とが所定比
になるように、前記非線型素子の順方向電圧の温
度係数と前記第5のトランジスタのベースエミツ
タ間電圧の温度係数とがほぼ等しく設定され、か
つ前記第1、第4の抵抗の抵抗値の積と前記第
3、第5の抵抗の抵抗値の積との比が決定されて
いることを特徴とする集積回路装置。
1 A flip-flop consisting of first and second transistors whose bases and collectors are alternately connected, and first and second load elements including nonlinear elements connected between their respective collectors and a signal line. and third and fourth transistors whose respective emitters are connected to the emitters of the first and second transistors, whose collectors are connected to the respective output terminals, and which are connected to the first power supply via a load resistor. A potential detection means including a transistor, and a second emitter.
a fifth transistor, whose base is connected to the second power source through the first resistor, whose collector is connected to the first power source through the second resistor, and whose emitter is connected to the third power source. is connected to the base of the fifth transistor via a resistor, the base is connected to the collector of the fifth transistor, and the collector is connected to the first transistor.
a power supply circuit consisting of a sixth transistor connected to the power supply of the sixth transistor; an emitter connected to the second power supply via a fourth resistor; a base connected to the emitter of the sixth transistor; and a collector connected to the sixth transistor. a reference potential generating circuit that includes a seventh transistor connected to the first power supply through a resistor No. 5, and supplies a reference potential to the bases of the third and fourth transistors; Temperature fluctuation and the first,
The temperature coefficient of the forward voltage of the nonlinear element and the temperature coefficient of the base-emitter voltage of the fifth transistor are set to be approximately equal so that the temperature variation of the potential drop due to the second load is at a predetermined ratio; The integrated circuit device is further characterized in that a ratio of the product of the resistance values of the first and fourth resistors to the product of the resistance values of the third and fifth resistors is determined.
JP13748178A 1978-11-08 1978-11-08 Integrated-circuit device Granted JPS5564684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13748178A JPS5564684A (en) 1978-11-08 1978-11-08 Integrated-circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13748178A JPS5564684A (en) 1978-11-08 1978-11-08 Integrated-circuit device

Publications (2)

Publication Number Publication Date
JPS5564684A JPS5564684A (en) 1980-05-15
JPS6135628B2 true JPS6135628B2 (en) 1986-08-14

Family

ID=15199628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13748178A Granted JPS5564684A (en) 1978-11-08 1978-11-08 Integrated-circuit device

Country Status (1)

Country Link
JP (1) JPS5564684A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168310A (en) * 1982-03-30 1983-10-04 Fujitsu Ltd Differential amplifying circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4099070A (en) * 1976-11-26 1978-07-04 Motorola, Inc. Sense-write circuit for random access memory

Also Published As

Publication number Publication date
JPS5564684A (en) 1980-05-15

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