JPH0320087B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schmitt circuit that outputs high and low output signals in response to an input signal, and to detect variations in the base-emitter voltage of a bias transistor for supplying a bias voltage to the Schmitt circuit. The present invention provides a zero-cross limit circuit that prevents a threshold voltage from varying from a zero-cross when an output signal is inverted.

FIG. 1 shows a conventional Schmitt circuit.

In Figure 1, R ₁ to _{R 11} are resistors, D ₁ is a diode, Q ₁ to _{Q 7} are transistors, C ₁ is a capacitor,
I ₀₁ and I ₀₂ are constant current sources with currents I ₀₁ and I ₀₂ , 1 is the input terminal, 2 is the power supply terminal, 3 is the output terminal, 4 is the ground terminal, A is the emitter of transistor Q ₁ , and B is the resistor.
The intersection of R ₅ and R ₇ , C is the base of transistor Q ₂ ,
D indicates the base of transistor _Q3 .

Now, the case where, for example, a triangular wave input signal shown in FIG. 3a is applied to the Schmitt circuit shown in FIG. 1 will be described with reference to FIG. 4.

In Fig. 1, when only the power supply voltage is applied between the 2nd and 4th terminals and no input signal is applied to 1st terminal, that is, during the period T ₁ shown in Fig. 4, a differential amplifier is configured. The base potentials V _c and V _D of the transistors Q ₂ and Q ₃ are V _c = V _D immediately after the power is turned on, but the resistance value of the resistor R ₁₁ and the collector current of the transistor Q ₆ drive the transistor Q ₇ . , transistor Q ₇ becomes conductive instantaneously, causing a voltage drop across resistor R ₆ . Therefore, if the potential at point A is V _A , the potential V _c at point C is: V _c = V _A - (R ₅ + R ₇ ) × I ₀₁ /h _FEQ2 ... (1) where h _FE Qn: Transistor Q Current amplification factor D of _o
The potential V _D at the point is expressed as V _D = V _A − I _c × R 6 (2), where I _c is the collector current of transistor Q ₇ , and I _c · _{R 6 >} (R ₅ + R ₇ )・I ₀₁ /h Since _FEQ2 , the base potentials of the differential transistors Q ₂ and Q ₃ are V _c ,
Since V _D becomes V _c >V _D , the output signal output to the third terminal is at a high level. Here R ₄ = R ₉ , R ₅
= R ₈ , R ₆ = R ₇ , h _FEQ2 = h _FEQ3 . In addition, above (1)
Since the input signal is superimposed on the V _c potential in equation (1),
Let the V _c potential in the equation be the reference potential, that is, the zero point.

Next, when an input signal is applied to one terminal, and considering the period T ₂ in Figure 4, the base potential of transistors Q ₂ and Q ₃ configuring the differential amplifier is
Since V _c and V _D always satisfy V _c ≧V _D , the output signal output to the three terminals is at the hay level.

Next, considering the period _T3 in FIG. 4, at the point where the base potential of transistors _Q2 and _Q3 constituting the differential amplifier changes from _Vc = _VD to _Vc < _VD , the transistor _Q7 becomes non-conductive and no collector current flows, so if the emitter current I _E of transistor Q ₁ and the current flowing through resistor R ₄ is I _R4 , then I _E = (I _R4 + I ₀₁ /h _FEQ2 ) + I _c ... From when Q ₇ is on (3), I _E = I _R4 + I ₀₁ /h _FEQ3 ... decreases when Q ₇ is off (4), so the base of transistor Q ₁
The emitter voltage is △V _BEQ1 = KT/qlnI _R4 +I ₀₁ /h _FEQ2 +I _c /I _R4 +I ₀₁ /
h _FEQ3 ...(5) becomes smaller and the potential at point A becomes (V _A + △V _BEQ1 ). Also, the potential V _D at point D is calculated from V _D shown in equation (2) (6)
V _D is shown in the formula.

V _D = V _A + △V _BEQ1 − (R ₆ + R ₈ ) × I ₀₁ /h _FEQ3 ...(6) Here, △V _BEQ1 is the base of transistor Q ₁ .
The change in the emitter voltage due to the change in the emitter current, K is the Boltzmann constant, T is the absolute temperature, and q is the amount of charge of the electron.

In this case, since the base potentials V _{c and} V _D of the transistors Q ₂ and Q ₃ constituting the differential amplifier become V _c <V _D , the output signal output to the three terminals is inverted to low level. At this time, the threshold voltage at which the output signal is inverted from high to low is the V _D potential shown in equation (2).

Next, considering the period T ₄ in Figure 4, the point where the base potentials V _{c and} V D _of the transistors Q ₂ and Q ₃ configuring the differential amplifier become V _c = V _D since V _c < V _D Since transistor Q ₇ conducts and collector current flows, the emitter current I _E of transistor Q ₁ becomes I _e = I _R4 + I ₀₁ /h _FEQ3 ...When Q ₇ is off (7), I _E = I _R4 +I ₀₁ /h _FEQ2 +I _c ......When Q ₇ is on (8), the voltage between the base and emitter of transistor Q ₁ is as follows: △V _BEQ1 = KT / qlnI _R4 +I ₀₁ /h _FEQ2 +I _c /I _R4 +I ₀₁
/h _FEQ3 ...(9) increases, so the potential at point A changes from V _A +△V _BEQ1 to V _A +△V _BEQ1 -△V _BEQ1 = V _A , and the potential at point D, V _D , becomes V _D = V _A +△V _BEQ1 − (R ₆ + R ₈ ) ×I ₀₁ /h _FEQ3 ……When Q ₇ is off (10), V _D = V _A −I _c ×R ₆ …… When Q ₇ is on (11), and the potentials of V _A and V _D return to the potentials during the T ₁ and T ₂ periods described above. In this case, the base potentials V _c and V _D of transistors Q ₂ and Q ₃ configuring the differential amplifier are
Since V _c > V _D , the output signal output to terminal 3 is inverted to high level. At this time, the threshold voltage at which the output signal is inverted from low to high is the V _D voltage shown in equation (6).

Here, if we compare the threshold voltage at which the output signal is inverted from low to high (V _D potential shown in equation (6)) with V _c potential (reference potential) shown in equation (1), , R ₅ = R ₈ , R ₇ = R ₆ , h _FEQ2 = h _FEQ3 , so V _c − V _D = {V _A − (R ₅ + R ₇ )・I ₀₁ /h _FEQ2 } − {V _A + △V _B
EQ1 −(R ₆ + R ₈ )・I ₀₁ /h _FEQ3 }=−△V _BEQ1 ……(12)
Therefore, there is a difference of △V _BEQ1 in the threshold voltage when the output signal is inverted from low to high, and zero crossing does not occur. When the input signal is very small, the inversion operation of the output signal from low to high becomes unstable, causing malfunction, which is inconvenient. Furthermore, T ₄
After the period, T ₂ , T ₃ , and T ₄ are repeated.

As mentioned above, the object of the present invention is to reduce the change from the zero crossing of the threshold voltage when the output signal in the prior art Schmitt circuit returns to its initial state when the output signal is inverted due to the fluctuation in the base-emitter voltage of the bias transistor. The object of the present invention is to obtain a zero-cross Schmitt circuit that eliminates fluctuations.

The simulator circuit according to the present invention has a simulator circuit in which a differential amplifier and a buffer circuit are connected in series and in which the output of the buffer circuit is positively fed back to the differential amplifier. a second transistor whose base and collector are commonly connected to the base and collector of the second transistor, a first resistor connected between the emitter of the first transistor and a reference point, the emitter of the second transistor and the the first
a second resistor having the same resistance value as the resistor; third and fourth resistors connected in series between the emitter of the first transistor and one input terminal of the differential amplifier; fifth and sixth resistors connected in series between the emitter of the transistor and the other input terminal of the differential amplifier, the third and sixth resistors having the same resistance value; The fourth and fifth resistors have the same resistance value, an input signal is supplied to a connection point between the third and fourth resistors, and the fifth and sixth resistors have the same resistance value.
The output of the buffer circuit is supplied to the connection point of the resistor.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 shows a zero-cross Schmitt circuit according to an embodiment of the present invention.

In Figure 2, R ₁ to _{R 12} are resistors, D ₁ is a diode, Q ₁ to _{Q 8} are transistors, C ₁ is a capacitor,
I ₀₁ and I ₀₂ are constant current sources with currents I ₀₁ and I ₀₂ , 1 is the input terminal, 2 is the power supply terminal, 3 is the output terminal, 4 is the ground terminal, A is the transistor Q, ₁ is the emitter, and B is the resistor.
The intersection of R ₅ and R ₇ , C is the base of transistor Q ₂ ,
D indicates the base of the transistor _Q3 , E indicates the emitter of the transistor _Q8 , and the common base of the F transistors _Q1 and _Q8 . Now, in the Schmitt circuit of the embodiment of the present invention shown in FIG.
The case where a triangular wave input signal shown in FIG. 5 is applied will be explained with reference to FIG.

In FIG. 2, when only the power supply voltage is applied between the 2nd and 4th terminals and no input signal is applied to 1st terminal, that is, during the period T ₁ shown in FIG.
Immediately after power-on, R ₄ = R ₁₂ and transistor Q ₂ ,
Since the base currents of Q ₃ are equal, transistors Q ₁ ,
Since the emitter currents I _EQ1 and I _EQ8 of Q ₈ are equal, V _A
= V _E , and the base potentials V _c and V _D of transistors Q ₂ and Q ₃ forming the differential amplifier are V _C = V _D
However, the resistance value of resistor R ₁₁ and transistor Q ₆
Because the collector current of transistor Q ₇ is large enough to drive transistor Q ₇ , transistor Q ₇ becomes conductive instantaneously, causing a voltage drop across resistor R _{6 .}
If the currents flowing through R ₄ and R ₁₂ are I _R4 and I _R12 , then the emitter current I _EQ1 flowing through the emitter of transistor Q ₁ is
I _EQ1 = I _R4 + I ₀₁ /h _FEQ2 (13) where h _FEQo : indicates the current amplification factor of the transistor Qn.

The potential V _A at point A is V _A = V _F - KT / qlnI _EQ1 / I _s ... (14) The potential V _c at point C is V _c = V _A - (R ₅ + R ₇ ) × I ₀₁ / h _FEQ2 ......(15) I _EQ8 = I _R12 + I _c ......When _Q7 is on (16) The potential V _E at point E is V _E = V _F -KT/qlnI _EQ8 /I _s ... (17) The potential V E at point D is The potential V _D is expressed as V _D = V _E −I _c ×R ₆ ……When Q ₇ is on (18). Here, I _R4 ≒ I _R12 ≒ I _c , I _E2 > I _E1 , V _A
> V _E , I _c R ₆ > (R ₅ + R ₇ )×I ₀₁ /h _FEQ2 , the base potentials V _c and V _D of transistors Q ₂ and Q ₃ become V _c > V _D , so three terminals The output signal output to is high level.

Here, K is Boltzmann constant, T is absolute temperature,
q indicates the amount of charge of electrons, and I _s indicates the saturation current. moreover
Let R ₄ = R ₉ = R ₁₂ , R ₅ = R ₈ , R ₆ = R ₇ , h _FEQ2 = h _FEQ3 . Note that since the input signal is superimposed on the V _c potential in equation (15) above, the V _c potential in equation (15) is set as a reference potential, that is, zero.

Next, when an input signal is applied to one terminal, and considering the period T ₂ in Figure 5, the base potential of transistors Q ₂ and Q ₃ configuring the differential amplifier
Since V _c and V _D are always V _c V _D , the output signal output to the three terminals is at a high level.

Next, considering the period T ₃ in Figure 5, at the point where the base potential of transistors Q ₂ and Q ₃ forming the differential amplifier changes from V _c = V _D to V _c < V _D , the transistor Q ₇ becomes non-conductive and no collector current flows, so the emitter current I _EQ8 flowing to the emitter of transistor Q ₈ is: I _EQ8 = I _R12 + I _c ...When Q ₇ is on (19), I _EQ8 = I _R12 + I ₀₁ /h _FEQ3 ...When _Q7 is off (20). Here, I _R4 = I _R12 , h _FEQ2 , so (20)
Equation = (13), and V _E = V _A. Also, the potential V _D at point D changes from V _D shown in equation (18) to V _D shown in equation (21).

V _D = V _E - (R ₆ + R ₈ ) × I ₀₁ /h _FEQ3 ... (21) In this case, the base potentials V _c and V _D of transistors Q ₂ and Q ₃ configuring the differential amplifier are V Since _c < V _D , the output signal output to terminal 3 is inverted to low level. At this time, the threshold voltage at which the output signal is reversed from high to low is shown in equation (18).
It is V _D.

Next, considering the period _T4 in FIG. 5, at the point where the base potential of transistors _Q2 and _Q3 constituting the differential amplifier becomes _Vc = _VD from _Vc < _VD , the transistor _Q7 conducts and collector current flows, so emitter current I _EQ8 flows to the emitter of transistor _Q8 .
becomes I _EQ8 = I _R12 + I ₀₁ /h _FEQ3 ...when _Q7 is off (22) to I _EQ8 +I _R12 +I _c ...when _Q7 is on (23), and the potential V _D at point D is V _D = V _E − (R ₆ + R ₈ ) × I ₀₁ /h _FEQ3 ...When Q ₇ is off (24), V _D = V _E −I _c × R ₆ ... When Q ₇ is on (25), and V _D The potential returns to the potential during the T ₁ and T ₂ periods. In this case, since the base potentials V _c and V _D of the transistors Q ₂ and Q ₃ forming the differential amplifier become V _c >V _D , the output signal outputted from the three terminals is inverted to a high level. At this time, the threshold voltage at which the output signal is reversed from low to high is shown in equation (21).
V _D potential. Here, the threshold voltage at which the output signal is inverted from low to high (shown in equation (21)) is
Comparing the V _D potential (V D potential) with the V _C potential (reference potential) shown in equation (15), R ₅ = R ₈ , R ₆ = R ₇ , h _FEQ2
= h _FEQ3 , V _A = V _E , so V _c −V _D = {V _A − (R ₅ + R ₇ )・I ₀₁ /h _FEQ2 } −{V _E − (R ₆ + R ₈ )・I ₀₁ /h _FEQ3 = 0 (26) When the output signal is inverted from low to high, there is no fluctuation in the threshold voltage and a zero cross occurs. Therefore, even when the input signal is very small, the inversion operation from low to high can be performed normally.

As described above, by using the zero-cross Schmitt circuit of the present invention, it is possible to realize a zero-cross Schmitt circuit that eliminates the fluctuation of the threshold voltage from the zero-cross when the output signal returns to its initial value.

Next, FIG. 6 shows another embodiment of the present invention. In FIG. 6, an embodiment is shown in which the transistors Q ₁ and Q ₈ shown in the embodiment of the present invention in FIG. 2 are replaced with a multi-emitter transistor Q ₁₁ having a common base and collector and two emitters. The other elements are the same.

It goes without saying that the same effect as that of the present invention can be obtained in FIG. 6 as well, as explained in FIG. 2. At this time, in order to ignore fluctuations in the potential V _F at point F due to the base currents of transistors Q ₁ , Q ₈ , and Q ₁₁ , resistors R ₁ , R ₂ , and R ₃ are made as small as possible within a practical range. I'll keep it.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional Schmitt circuit, Figure 2 is a circuit diagram showing an embodiment of the Schmitt circuit of the present invention, and Figure 3 shows the input/output characteristics of Figures 1 and 2. 4 is a diagram showing details of the operation of FIG. 1, FIG. 5 is a diagram showing details of the operation of FIG. 2, and FIG. 6 is a circuit diagram showing another embodiment of the present invention. be. R ₁ to R ₁₂ are resistors, D ₁ is a diode, Q ₁ to _{Q 8} ,
Q ₁₁ is a transistor, C ₁ is a capacitor, I ₀₁ and I ₀₂ are constant current sources, 1 to 4 are terminals, and A to F each bias point.

Claims (1)

[Claims] 1. In a Schmitt circuit in which a differential amplifier and a buffer circuit are connected in series and the output of the buffer circuit is positively fed back to the differential amplifier, a first transistor whose base is supplied with a bias voltage, and a base and a collector of this transistor are connected to each other. and a second transistor whose collectors are commonly connected, a first resistor connected between the emitter of the first transistor and the reference point, and a first resistor connected between the emitter of the second transistor and the reference point. a second resistor connected and having the same resistance value as the first resistor;
a resistor, third and fourth resistors connected in series between the emitter of the first transistor and one input terminal of the differential amplifier, and the second resistor.
fifth and sixth resistors connected in series between the emitter of the transistor and the other input terminal of the differential amplifier, the third and sixth resistors having the same resistance value; The fourth and fifth resistors have the same resistance value, an input signal is supplied to a connection point between the third and fourth resistors, and a connection point between the fifth and sixth resistors is supplied with the buffer circuit. A Schmidt circuit characterized in that an output is provided.