JPS6136666B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer storage device for a data processing device, and more particularly to a buffer storage device for controlling data transfer.

In general, for high-speed logical devices, main memory has a large capacity but is slow, so to minimize this speed gap, a logical device that stores a portion of the data in main memory is used. Providing equally fast buffer storage is widely adopted. The data memory in this buffer storage device stores the data in the main storage device in units of blocks of about 32 bytes in length, and if the desired data does not exist in the buffer storage device, the data is stored in units of blocks. Access to main storage is made. The block transfer performed from the main memory to the buffer storage by this access is generally performed by time-divisionally transferring 8-byte data four times.

Conventionally, this type of buffer storage device was in a busy state in which it did not accept access from the next new logical device until all the block data transferred in four time divisions had been stored in the data memory. During this time, the logic device had the disadvantage of being in a waiting state.

As a method to solve this drawback, a method of providing a data buffer is known. That is, by temporarily storing the block data transferred from the main memory in the data buffer and moving the contents of the data buffer to the data memory when the buffer memory is free, the data can be transferred from the logical device to the buffer memory even during block transfer. I know of a way to enable access. However, in this solution, a management table is provided for the data memory and has address information in the main memory of each block that is the contents of the data memory and a validity bit indicating the validity of each block. This had the disadvantage of increasing the amount of hardware since it had to be provided separately.

An object of the present invention is to solve the above-mentioned drawbacks by adding a storage position indicating bit in the management table memory provided for the data memory to indicate whether the contents of each block exist in the data memory or the data buffer. However, it is an object of the present invention to provide a buffer storage device that can accept access from a logical device even during block transfer from a main storage device with a minimum increase in the amount of hardware.

The buffer storage device of the present invention includes a data memory that stores part of the storage contents of the main storage device in block units, a data buffer that temporarily stores transfer blocks from the main storage device, and each block in the data memory. address information indicating the storage location in the main memory for each block; validity bit information indicating that the contents of each block in the data memory or the data buffer are valid; and the contents of each block. A management table memory that stores storage position display bit information indicating where the block exists in the data buffer or the data memory, and the block accessed when the main memory access occurs is indicated as valid by the validity bit information. If so, either the read data from the data memory or the data buffer is selected as desired data according to the storage position display bit information, and when a block transfer from the main memory occurs, the transferred block data is is temporarily stored in the data buffer, and the valid data in the data buffer is controlled to be transferred to the data memory during free time.

The present invention eliminates the influence of the time required for block transfer from the main storage device to the buffer storage device on the data processing speed by providing the data buffer, and also provides the data storage system in the management table memory provided for the data memory. By adding the position display bit information, a management table corresponding to the data buffer and a reference control circuit for this management table can be made unnecessary.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a circuit configuration diagram of a device according to an embodiment of the present invention.
In the figure, a logical device 1 and a main storage device 2 are configured via a buffer storage device 3. The buffer storage method in this embodiment employs a set associative method with 64 sets, 2 compartments, and a block length of 32 bytes, and block transfer from the main storage device 2 to the buffer storage device 3 is performed per access. Although time-division transfer of 8 bytes each is performed four times, other methods may be adopted.

The buffer storage device 3 includes an address register 5,
data memory 6, data buffer 7, management table memory 8, comparison circuit 9, selection circuits 10, 11,
buffer address register 12, addition circuit 14,
15, selection circuits 16, 17, 18, a write address register 20, and a control circuit 21.

The data memory 6 stores a part of the storage contents of the main storage device 2 in units of 32-byte blocks,
The read/write data width per access is 8 bytes for each compartment. The data buffer 7 temporarily stores transfer blocks from the main memory 2 and has a 4 word x 8 byte configuration, and can read and write at the same time by using a widely known register file. can.

The management table memory 8 also includes the data memory 6.
Bits 8 to 20 of the address indicate the storage location of each block in the main memory device 2 corresponding to each block in the block.
address memory _8-1 for storing the data, a validity bit indicating whether the contents of each block are the same as the contents stored in the main memory 2, and whether the contents of each block exist in the data memory 6 or the data buffer 7. and a management memory _8-2 for storing a storage position indicating bit indicating whether or not the data is to be stored.

In addition, the comparison circuit 9 is connected to the address memory _8-1-2 .
Each compartment output is compared with bits 8 to 20 of address register 5. Further, the selection circuit 10 selects the output of the two compartments of the data memory 6 for which the comparison circuit 9 detects a match. Further, the selection circuit 11 selects the selection circuit 1 according to the storage position display bit in the management memory _8-2 .
0 or data buffer 7 is selected.

The buffer address register 12 also stores a 6-bit address indicating the storage location in the data memory 6 corresponding to the block in the data buffer 7. Addition circuits 14 and 15 also add ``+1'' to the 2-bit input address information modulo ``4'' (that is, add ``0'' when the addition result is ``4''). , outputs the 2-bit addition result. Also, write address register 20
supplies a write address to the data buffer 7. The read address for this data buffer 7 is supplied with bits 27 and 28 of the address register 5. Further, the control circuit 21 is configured to perform communication for access control between the logic device 1 and the main memory device 2 and control each circuit within the buffer memory device 3.

Next, this embodiment will be explained according to operations in various cases. In the following explanation, when it is determined that the desired data exists in the data memory 6 or the data buffer 7 as "valid" as a result of referring to the validity bit in the management memory _8-2 during access from the logical device 1, it will be referred to as "FB". '', and conversely, the case where the desired data found to be invalid must be accessed to the main storage device 2 and fetched is called ``NFB''. Furthermore, the following (i=1, 2,
3, . . . ) represent machine cycle numbers, each description represents an operation for one machine cycle, and the value represents the order in the timing sequence.

[In the case of FB] By referring to the storage position display bit, which is the output of the management memory _8-2 , in the control circuit 21,
The output of the selection circuit 10, which is the output of the data memory 6, or the output of the data buffer 7 is selected by the selection circuit 11, and desired data is transferred to the logic device 1.

[For NFB]

The block stored in data buffer 7 by the previous NFB is changed to block A, and the block stored in data buffer 7 by the previous NFB is
Let the block that has become NFB be Block B.

In the control circuit 21, an access request is generated to the main memory 2, one of the two compartments is selected by a replacement algorithm known in the prior art, and the selected compartment in the management table memory 8 is stored. Bits 8~ of the output of address register 5
20 is stored, and these two bits are stored with polarity such that the validity bit indicates valid and the storage position indicating bit indicates the data buffer.
(Request to read block B to main memory 2 and registration of information for block B in management table memory 8) Bits 21 to 26 of the output of address register 5 are sent to buffer address register 12, and The output is stored in bits 21 to 26 of address register 5 via selection circuit 16 in such a way that the contents of each 6 bits of both registers 5 and 12 are exchanged, and bits 27 and 28 of the output of address register 5 are written. Store in address register 20. (Thus, bits 21 to 26 of address register 5 indicate the address for block A, the contents of buffer address register 12 indicate the address for block B, and write address register 2 indicates the address for block A.)
The content of 0 indicates the position of the first 8-byte data block transferred from the main storage device 2 in block B. ) Using bits 27 and 28 of the output of the address register 5 as read address inputs, one word or 8 bytes of data in the data buffer 7 is read out and stored in the data memory 6. The storage location of the data memory 6 is determined by using the outputs 21 to 26 of the address register 5 as address inputs to the management memory 8.
₂ is read out, and the control circuit 21 instructs the data memory 6 to select the compartment in which the storage position indicating bit indicates the data buffer.
Bits 21 to 28 of the output of address register 5 become the write address of data memory 6. (Transfer from data buffer 7 of block A to data memory 6. For 8 bytes.) Furthermore, bits 27 and 28 of the output of address register 5 are added by "+1" in addition circuit 14, and the addition result is sent via selection circuit 17. and stored in bits 27 and 28 of address register 5.

Performs the same operation as .

Performs the same operation as .

The same operation as above is performed, and the storage position indicating bit is stored in the management memory _8-2 with a polarity indicating that block A exists in the data memory 6. (Operation completed.) Main storage device 2
The read operation in the main memory device 2 is completed by accessing the data buffer 7 from the main memory device 2.
After waiting for block transfer to start, perform the following operations.

(n is an integer of 6 or more) The 8 bytes of transfer data from the main storage device 2 are stored in the address position indicated by the output of the write address register 20 in the data buffer 7, and the output of the write address register 20 is further added to the adder circuit. Add “+1” at 15,
The addition result is stored in the write address register 20 via the selection circuit 18. (Storing block B to data buffer 7. 8 bytes.) Performs the same operation as 〓n+1〓 and also stores bits 27 and 28 of the output of address register 5 (since these 2 bits were set to ``+1'' four times by ~, After that, it returns to the value when the access request was made from the original logical device 1. - Therefore, as mentioned above, n must be 6 or more.)
The output of the data buffer 7 is transferred to the logic device 1 via the selection circuit 11 with the read address as the read address, and the operation in the logic device 1 is restarted.

Perform the same operation as 〓n+2〓 and 〓n+3〓.

Regarding the value of n mentioned above, since a read operation in the main memory device 2 normally takes about 10 machine cycles, n
≧6 is acceptable.

In this embodiment, the capacity of the data buffer 7 is set to one block, that is, 32 bytes, but since the data buffer 7 has a shorter read time than the data memory 6, one block is held in the data buffer 7 for as long as possible. If you want to keep the capacity of the data buffer 7 for multiple blocks, you can have multiple sets of buffer address registers 12 for the number of blocks.
This can easily be done by adding a bit in ₂ to indicate where in the data buffer 7 the corresponding block is located.

In the conventional system with a data buffer, the number of bits in the buffer address register 12 corresponding to the data buffer 7 needs to be the same as the upper 13 bits of the address, and a comparison circuit similar to the comparison circuit 9 is also attached to the buffer address register 12. However, in the present invention, the above circuit is significantly reduced.

As explained above, by newly adding a storage position display bit in the management table memory, the buffer storage device is not in a busy state even during block transfer from the main storage device. This has the excellent effect of minimizing the amount of metal required.

[Brief explanation of the drawing]

The figure is a circuit configuration diagram of a device according to an embodiment of the present invention. 1...Logic device, 2...Main storage device, 3...Buffer storage device, 5...Address register, 6...
...Data memory, 7...Data buffer, 8...
Management table memory, 8- ₁ ... Address memory, 8- ₂ ... Management memory, 9 ... Comparison circuit, 1
0, 11... Selection circuit, 12... Buffer address register, 14, 15... Addition circuit, 16, 1
7, 18...Selection circuit, 20...Write address register, 21...Control circuit.

Claims (1)

[Claims] 1. A data memory that stores part of the storage contents of the main storage device in block units, a data buffer that temporarily stores transfer blocks from the main storage device in block units of one or more blocks, and a data memory that stores part of the storage contents of the data memory in block units. Address information provided corresponding to each block and indicating the storage location in the main memory for each block, validity bit information indicating that the contents of each block in the data memory or the data buffer are valid, and each block. and a management table memory for storing storage position indicating bit information indicating where in the data buffer or in the data memory the contents of the data exist, and when the main memory access occurs, the desired data is stored in the management table memory. If the data is in a block that is validly displayed according to the validity bit information, select either the data memory or successive data from the data buffer according to the storage position display bit information and set it as desired data;
If the validity bit information is displayed as invalid, an access is made to the main memory, the block data transferred from the main memory by this access is temporarily stored in the data buffer, and then the free time is used to store the block data in the data buffer. A buffer storage device comprising: control means for transferring valid data in the data memory to the data memory.