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JPS6136704B2 - - Google Patents
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JPS6136704B2 - - Google Patents

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Publication number
JPS6136704B2
JPS6136704B2 JP54033745A JP3374579A JPS6136704B2 JP S6136704 B2 JPS6136704 B2 JP S6136704B2 JP 54033745 A JP54033745 A JP 54033745A JP 3374579 A JP3374579 A JP 3374579A JP S6136704 B2 JPS6136704 B2 JP S6136704B2
Authority
JP
Japan
Prior art keywords
chip
mark
camera
signal
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54033745A
Other languages
Japanese (ja)
Other versions
JPS55125641A (en
Inventor
Masayuki Naruse
Shige Yamada
Isao Tokumaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3374579A priority Critical patent/JPS55125641A/en
Publication of JPS55125641A publication Critical patent/JPS55125641A/en
Publication of JPS6136704B2 publication Critical patent/JPS6136704B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 本発明は半導体チツプ等の製造工程のうち、チ
ツプの判定マークを検出しそのマークのあるチツ
プを自動的に取り除くチツプ自動選別装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic chip sorting device that detects a judgment mark on a chip and automatically removes chips with the mark during the manufacturing process of semiconductor chips and the like.

従来の半導体チツプ製造における選別工程は、
各チツプを切り離さないウエハの状態で、まずウ
エハローバで電気検査を行い不良チツプについて
はチツプの中央付近にVの字型の不良マークある
いはレーザの照射による痕跡をつけ、しかる後ウ
エハを透明なシートにのせスクライバで各々のチ
ツプの四辺にすべて割れ目をつけ、その上にさら
にシートをかぶせてサンドイツチしたウエハを押
圧ローラで押えて各々のチツプをチツプ単位に分
離する。次にウエハの上にかぶせたシートを取り
はずし、リング状の治具にのせリング状治具から
はみ出ているシートを保持して引伸し拡大する。
これにより各チツプはシート上に互いに間隔を空
けてマトリツクス状に整列する。この状態で、従
来は目視作業により不良マークのしるされたチツ
プをシートから取り除く作業を行つていたが、人
手に頼るため作業能率が悪く、さらに単純な作業
のためこの目視作業の自動化が強く望まれてい
た。
The sorting process in conventional semiconductor chip manufacturing is
With each chip unseparated, the wafer is first electrically inspected using a wafer rover, and for defective chips, a V-shaped defective mark or laser irradiation mark is placed near the center of the chip, and then the wafer is placed on a transparent sheet. A scriber is used to create cracks on all four sides of each chip, a sheet is placed over the cracked wafer, and the sandwiched wafer is pressed down with a pressure roller to separate each chip into individual chips. Next, the sheet placed over the wafer is removed, placed on a ring-shaped jig, and the sheet protruding from the ring-shaped jig is held and enlarged.
As a result, the chips are arranged in a matrix on the sheet at intervals from each other. In this state, chips with defective marks were conventionally removed from the sheet by visual inspection, but the work was inefficient as it relied on manual labor, and since the task was simple, it was difficult to automate this visual inspection. It was strongly desired.

このように本発明の目的はリング状治具上に引
伸ばされたチツプ群からマーク、例えば不良マー
クのしるされたチツプを迅速に見つけ出しこれを
取り除くチツプ自動選別装置を提供することにあ
る。
SUMMARY OF THE INVENTION Thus, an object of the present invention is to provide an automatic chip sorting device that quickly finds and removes chips with marks, for example, defective marks, from a group of chips stretched on a ring-shaped jig.

この目的を達成するために本発明によるチツプ
自動選別装置は、チツプ1個を真上から落射照明
する照明系と、そのチツプを適当な倍率で拡大す
る光学系を有しその光学像を映像信号に光電変換
するカメラと、光学像をカメラに入力するときシ
ート上のチツプを先端が平坦な軸で下から押し上
げカメラの真下のチツプを光学系と直角に位置を
出すとともに周囲のチツプに傾斜を与えるチツプ
押し上げ機構と、チツプ位置検出時には位置誤差
を考慮して少くとも1チツプの全域を含む範囲に
またマーク検出時には1チツプの外周よりやや内
側の範囲についてカメラから映像信号を出力する
ようにしたスキヤンエリア設定回路と、前記映像
信号を適当な閾値で“1”または“0”に2値化
する2値化回路と、対象チツプの大きさや基準の
位置等の情報を記憶する基準情報設定回路と、そ
こに記憶されているチツプの大きさや位置等の情
報を2値化後のチツプの信号と比較しX方向,Y
方向および回転のずれ量を算出する位置検出回路
と、そこで算出されたずれ量ΔX,ΔY,ΔΘに
応じてXYΘテーブルを駆動しチツプを基準の位
置に位置決めするチツプ位置決め回路と、チツプ
外周よりやや内側の領域の2値化信号からチツプ
にしるされたマークの有無を検出するマーク検出
回路と、前記2値化信号をチツプ位置検出時には
位置検出回路にまたマーク検出時にはマーク検出
回路に送る切替回路と、前記チツプ押し上げ機構
とマークが検出されればそのチツプを取り除くチ
ツプ排除機構とを制御する機構制御部と、前記す
べてをシーケンスコントロールする制御部とから
構成されている。
In order to achieve this object, the automatic chip sorting device according to the present invention has an illumination system that epi-illuminates one chip from directly above, and an optical system that magnifies the chip at an appropriate magnification, and converts the optical image into a video signal. When inputting an optical image to the camera, the chip on the sheet is pushed up from below with a shaft with a flat tip, positioning the chip directly below the camera at right angles to the optical system, and tilting the surrounding chips. When detecting the chip position, the camera outputs a video signal for a range that includes at least the entire area of one chip, taking into account position errors, and for a range slightly inside the outer circumference of one chip when detecting a mark. A scan area setting circuit, a binarization circuit that binarizes the video signal into "1" or "0" with an appropriate threshold value, and a reference information setting circuit that stores information such as the size of the target chip and the reference position. The information stored therein, such as the size and position of the chip, is compared with the chip signal after binarization, and the information in the X direction and Y direction is compared.
A position detection circuit that calculates the amount of deviation in direction and rotation, a chip positioning circuit that drives an a mark detection circuit that detects the presence or absence of a mark marked on a chip from a binary signal in the inner region; and a switching circuit that sends the binary signal to the position detection circuit when detecting the chip position and to the mark detection circuit when detecting a mark. , a mechanism control unit that controls the chip pushing up mechanism and a chip removal mechanism that removes the chip when a mark is detected, and a control unit that sequence controls all of the above.

本発明の構成によれば、リング状治具の上に多
数個載せられたチツプを自動的に位置決めしその
中からマークのついたチツプを自動的に取り除く
ことができる。
According to the configuration of the present invention, it is possible to automatically position a large number of chips placed on a ring-shaped jig and to automatically remove chips with marks therefrom.

以下本発明を半導体チツプの不良チツプを自動
選別する場合について図面を参照して詳しく説明
する。第1図は本発明による装置の構成を示すブ
ロツク図である。第2図は第1図においてチツプ
を照射する照明系を説明する図で、第3図はカメ
ラに取り込まれる映像を段階的に示す図である。
第1図において、半導体チツプ3が多数個マトリ
ツクス状に整列したリング状治具2をXYΘテー
ブル11に載置すると、制御部30からの指令に
よりチツプ位置決め回路10が動作し、まずウエ
ハ端部の最初のチツプがカメラ下の中央部に概略
位置決めされる。次に第2図に示すようにシート
の下から前記チツプ3を先端が平坦でチツプ3の
外径とほぼ同じ面積の軸端104で押し上げる。
押し上げられたチツプ3はカメラおよび照明系の
光軸と直角に規正されるとともにチツプ3の周囲
のチツプ3′およびチツプ3に近接したシート1
に傾斜が与えられる。このためチツプ3の表面に
当つた照明光はそのまま反射しレンズ23および
ハーフミラー22を介してカメラにチツプの光学
像として導入されるのに対し、チツプ3の周囲の
シートの表面反射およびチツプ3に近接したチツ
プ3′からの照明光の反射はカメラの光軸とある
傾きをもつて反射しカメラには鮮明な光学像とし
て導かれない。すなわち検査対象のチツプ3のみ
の像が明瞭に写し出され周囲のその他のチツプや
シートの像が不鮮明となり目的とするチツプ3の
像が他から浮き出た状態になる。このチツプ3の
光学像がカメラ50の光電変換面に導入される。
この時スキヤンエリア設定回路40は検査対象の
チツプを最低限含むに足る面積のみの信号をカメ
ラ50が光電変換しその他の信号は無視するよう
に構成してある。さらに光電変換するスキヤンエ
リアの設定は第3図の1に示すように、チツプの
整列不揃いによる位置のばらつきやリング状治具
の位置決め誤差を含めて少くとも1個のチツプが
完全に含まれる四辺形41とし、この四辺形41
の中に2個のチツプの全面が同時に含まれない範
囲に設定してある。第1図にもどり、このように
カメラ50からの映像信号はただちに2値化回路
60に送られ適当な閾値で“1”または“0”に
2値化される。このデジタルに変換された信号は
切換回路70を位置検出回路80に接続すること
により順次位置検出回路80に送られる。位置検
出回路80では、信号が“0”から“1”に変化
する点の軌跡で構成された直線が四辺形を形成す
るか否かによつて他のチツプやノズル等の信号を
除去し、得られた四辺形を基準情報設定回路81
に予め記憶されているチツプの大きさおよび基準
位置の標準データと比較演算することにより基準
位置からのチツプの位置偏差ΔX,ΔY,ΔΘが
演算される。チツプ3の位置検出が終ると直ちに
前記チツプ押し上げ機構101が下降するととも
に、計算された位置偏差が制御部30からチツプ
位置決め回路10に送られXYΘテーブル11を
駆動して、第3図の2に示すようにチツプの位置
が補正される。引続きこのチツプ3に不良マーク
4が付けられているか否か検出するため、スキヤ
ンエリア設定回路40により、第3図の3に示す
ようにチツプ3の外周部よりやや小さい四辺形の
領域42についてカメラ50が出力するようにし
ておき、前述と同様2値化信号を順次マーク検出
回路90に入力させる。マーク検出回路90では
不良マーク4の特徴である斜線の有無を検出する
と直ちにチツプ3が不良か否かが判定される。こ
の判定結果が制御部30に送られ不良チツプであ
れば機構制御部100により前記チツプ押し上げ
機構101を動作させチツプ3をシート1から少
し突き上げチツプ3が上から取り易い状態にして
おき、次に先端に吸着ノズル103を設けたチツ
プ排除機構102が動作し不良チツプをシート1
から取り除く。不良チツプでなければXYΘテー
ブル11が次のチツプに移動し前記動作を繰り返
してリング状治具2に載置されているすべてのチ
ツプについてこの動作を繰り返すことにより、不
良チツプがすべて取り除かれる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings regarding the automatic selection of defective semiconductor chips. FIG. 1 is a block diagram showing the configuration of an apparatus according to the present invention. FIG. 2 is a diagram for explaining the illumination system for illuminating the chip in FIG. 1, and FIG. 3 is a diagram showing step-by-step images captured by the camera.
In FIG. 1, when a ring-shaped jig 2 in which a large number of semiconductor chips 3 are arranged in a matrix is placed on an The first chip is roughly positioned in the center below the camera. Next, as shown in FIG. 2, the tip 3 is pushed up from under the sheet with a shaft end 104 that has a flat tip and has approximately the same area as the outside diameter of the tip 3.
The pushed up chip 3 is oriented perpendicular to the optical axis of the camera and illumination system, and the chip 3' surrounding the chip 3 and the sheet 1 near the chip 3
is given a slope. Therefore, the illumination light that hits the surface of the chip 3 is directly reflected and is introduced into the camera as an optical image of the chip via the lens 23 and the half mirror 22. The illumination light reflected from the chip 3' close to the chip 3' is reflected at a certain angle to the optical axis of the camera, and is not guided to the camera as a clear optical image. That is, the image of only the chip 3 to be inspected is clearly projected, the images of other chips and sheets around it become unclear, and the image of the target chip 3 stands out from the others. This optical image of the chip 3 is introduced to the photoelectric conversion surface of the camera 50.
At this time, the scan area setting circuit 40 is configured so that the camera 50 photoelectrically converts only the signals of an area sufficient to include at least the chip to be inspected, and other signals are ignored. Furthermore, the scan area for photoelectric conversion is set on four sides that completely contain at least one chip, including positional variations due to uneven chip alignment and positioning errors of the ring jig, as shown in 1 in Figure 3. Let the shape be 41, and this quadrilateral 41
The range is set so that the entire surfaces of two chips are not included at the same time. Returning to FIG. 1, the video signal from the camera 50 is immediately sent to the binarization circuit 60 and binarized into "1" or "0" using an appropriate threshold. This digitally converted signal is sequentially sent to the position detection circuit 80 by connecting the switching circuit 70 to the position detection circuit 80. The position detection circuit 80 removes signals from other chips, nozzles, etc. depending on whether the straight line formed by the locus of points where the signal changes from "0" to "1" forms a quadrilateral. The obtained quadrilateral is used as a reference information setting circuit 81.
The positional deviations ΔX, ΔY, and ΔΘ of the chip from the reference position are calculated by comparing and calculating the size of the chip and standard data of the reference position stored in advance. Immediately after the detection of the position of the chip 3 is completed, the chip lifting mechanism 101 descends, and the calculated positional deviation is sent from the control section 30 to the chip positioning circuit 10, which drives the XYΘ table 11. The chip position is corrected as shown. Subsequently, in order to detect whether or not a defective mark 4 is attached to this chip 3, the scan area setting circuit 40 sets the camera to a quadrilateral area 42 that is slightly smaller than the outer periphery of the chip 3, as shown in 3 in FIG. 50 is outputted, and the binary signals are sequentially input to the mark detection circuit 90 in the same way as described above. As soon as the mark detection circuit 90 detects the presence or absence of diagonal lines, which is a characteristic of the defective mark 4, it is determined whether the chip 3 is defective or not. This judgment result is sent to the control unit 30, and if the chip is defective, the mechanism control unit 100 operates the chip pushing up mechanism 101 to push the chip 3 up a little from the sheet 1 so that the chip 3 can be easily removed from above. A chip removal mechanism 102 equipped with a suction nozzle 103 at the tip operates to remove defective chips from the sheet 1.
remove from If it is not a defective chip, the XYΘ table 11 moves to the next chip and repeats the above operation for all the chips placed on the ring-shaped jig 2, thereby removing all the defective chips.

本発明は以上のように構成してあるからその効
果として、まずリング治具に塔載されたすべての
チツプから不良チツプを自動的に取り除くことが
可能になり、従来人手に頼つていた作業を無人化
することができる。次にチツプの位置検出におい
てシート下部から検査対象チツプをわずかに持ち
上げるので、検出対象チツプ以外の像がほとんど
カメラに入力されないのでコントラストの良い映
像が得られ、その後の2値化あるいは位置検出回
路が簡単に構成できる。さらにカメラからの映像
出力領域を必要最小限に小さくしているので信号
処理の時間が短くて済む等秀れた利点がある。
Since the present invention is configured as described above, one of its effects is that it becomes possible to automatically remove defective chips from all the chips mounted on the ring jig, which is a work that previously had to be done manually. can be unmanned. Next, during chip position detection, the chip to be inspected is slightly lifted from the bottom of the sheet, so almost no images other than the chip to be detected are input to the camera, resulting in a high-contrast image that can be used for subsequent binarization or position detection circuits. Easy to configure. Furthermore, since the video output area from the camera is reduced to the minimum necessary size, there are excellent advantages such as short signal processing time.

以上説明したように本発明は半導体組立工程に
おいて自動化を阻害していたチツプの自動選別が
可能になりその効果は極めて大きい。
As explained above, the present invention enables the automatic selection of chips, which has hindered automation in the semiconductor assembly process, and its effects are extremely large.

なお本発明は、不良チツプを取り除くことで説
明したが、逆に良品チツプを別のシートに置きか
えるように構成しても本発明に含まれることは言
うまでもない。また以上の説明は主として半導体
チツプの良否の自動選別装置に適用して行つた
が、本発明は他の自動選別装置としても用いられ
ることは勿論である。
Although the present invention has been described by removing defective chips, it goes without saying that the present invention also includes a configuration in which good chips are replaced with another sheet. Furthermore, although the above description has been mainly applied to an automatic sorting apparatus for determining whether semiconductor chips are good or bad, it goes without saying that the present invention can also be used for other automatic sorting apparatuses.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による装置の構成を示すブロツ
ク図で、第2図は第1図の照明系の部分拡大図、
第3図はカメラに取り込まれる映像を示す図、1
は検査対象チツプにずれがある状態、2はずれが
修正された状態、3はマークを検出している状態
を示している。 1……シート、2……リング状治具、3……チ
ツプ、10……チツプ位置決め回路、11……
XYΘテーブル、21……照明ランプ、23……
レンズ、30……制御部、40……スキヤンエリ
ア設定回路、50……カメラ、60……2値化回
路、70……切替回路、80……位置検出回路、
81……基準情報設定回路、90……マーク検出
回路、100……機構制御部、101……押し上
げ機構、102……チツプ排除機構。
FIG. 1 is a block diagram showing the configuration of an apparatus according to the present invention, and FIG. 2 is a partially enlarged view of the illumination system in FIG.
Figure 3 is a diagram showing the image captured by the camera, 1
2 indicates a state in which the chip to be inspected is misaligned, 2 indicates a state in which the misalignment has been corrected, and 3 indicates a state in which a mark is being detected. 1... Sheet, 2... Ring-shaped jig, 3... Chip, 10... Chip positioning circuit, 11...
XYΘ table, 21... lighting lamp, 23...
Lens, 30...Control unit, 40...Scan area setting circuit, 50...Camera, 60...Binarization circuit, 70...Switching circuit, 80...Position detection circuit,
81... Reference information setting circuit, 90... Mark detection circuit, 100... Mechanism control section, 101... Pushing up mechanism, 102... Chip removal mechanism.

Claims (1)

【特許請求の範囲】[Claims] 1 チツプを真上から落射照明する照明系と、そ
のチツプを適当な倍率で拡大する光学系を有しそ
の光学像を映像信号に光電変換するカメラと、光
学像をカメラに入力するときシート上のチツプを
先端が平坦な軸で下から押し上げカメラの真下の
チツプを光学系と直角に位置を出すとともに周囲
のチツプに傾斜を与えるチツプ押し上げ機構と、
チツプ位置検出時には少くとも1個のチツプの全
面積を含む範囲にまたマーク検出時には1チツプ
の外周よりやや内側の面積についてカメラからの
映像信号を出力するようにしたスキヤンエリア設
定回路と、前記映像信号を適当な閾値で“1”ま
たは“0”に2値化する2値化回路と、対象チツ
プの大きさや基準の位置等の情報を記憶する基準
情報設定回路と、そこに記憶されている基準情報
を2値化後のチツプの信号と比較しX方向,Y方
向および回転のずれ量を算出する位置検出回路と
この算出されたずれ量に応じてXYΘテーブルを
駆動しチツプを基準の位置に位置決めするチツプ
位置決め回路と、チツプ外周よりやや内側の領域
の2値化信号からチツプにしるされたマークの有
無を検出するマーク検出回路と、前記2値化信号
をチツプ位置検出時には位置検出回路にまたマー
ク検出時にはマーク検出回路に送る切替回路と前
記チツプ押し上げ機構とマークが検出されればそ
のチツプを取り除くチツプ排除機構とを制御する
機構制御部と、前記すべてをシーケンスコントロ
ールする制御部とから構成したことを特徴とする
チツプ自動選別装置。
1. An illumination system that epi-illuminates the chip from directly above, a camera that has an optical system that magnifies the chip at an appropriate magnification and photoelectrically converts the optical image into a video signal, and a chip pushing mechanism that pushes up the chip from below with a shaft with a flat tip, positions the chip directly below the camera at right angles to the optical system, and tilts the surrounding chips;
a scan area setting circuit configured to output a video signal from a camera to a range including the entire area of at least one chip when detecting a chip position, and to an area slightly inside the outer periphery of one chip when detecting a mark; A binarization circuit that binarizes a signal into "1" or "0" with an appropriate threshold value, a reference information setting circuit that stores information such as the size of the target chip and the reference position, and the information stored therein. A position detection circuit that compares the reference information with the chip signal after binarization and calculates the amount of deviation in the X direction, Y direction, and rotation, and drives the XYΘ table according to the calculated amount of deviation to place the chip in the reference position. a mark detection circuit that detects the presence or absence of a mark on the chip from a binary signal in an area slightly inside the outer periphery of the chip; and a position detection circuit that detects the chip position using the binary signal. and a mechanism control unit that controls a switching circuit that sends the signal to the mark detection circuit when a mark is detected, the chip pushing mechanism, and a chip removal mechanism that removes the chip when a mark is detected, and a control unit that sequence-controls all of the above. An automatic chip sorting device characterized by the following configuration.
JP3374579A 1979-03-22 1979-03-22 Automatic chip selection apparatus Granted JPS55125641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3374579A JPS55125641A (en) 1979-03-22 1979-03-22 Automatic chip selection apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3374579A JPS55125641A (en) 1979-03-22 1979-03-22 Automatic chip selection apparatus

Publications (2)

Publication Number Publication Date
JPS55125641A JPS55125641A (en) 1980-09-27
JPS6136704B2 true JPS6136704B2 (en) 1986-08-20

Family

ID=12394945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3374579A Granted JPS55125641A (en) 1979-03-22 1979-03-22 Automatic chip selection apparatus

Country Status (1)

Country Link
JP (1) JPS55125641A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258482A (en) * 2006-03-23 2007-10-04 Fujitsu Ltd Inspection apparatus and inspection method for semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5897844A (en) * 1981-12-07 1983-06-10 Shinkawa Ltd Die repacking device
JPS58165339A (en) * 1982-03-26 1983-09-30 Nec Corp Method and device for mounting semiconductor pellet thereof
JPS59211239A (en) * 1983-05-17 1984-11-30 Nec Corp Semiconductor pellet arraying machine
JPS6127652A (en) * 1984-07-18 1986-02-07 Shinkawa Ltd Wafer positioning device
SG148902A1 (en) * 2007-07-09 2009-01-29 Generic Power Pte Ltd Die ejector with illuminating unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007258482A (en) * 2006-03-23 2007-10-04 Fujitsu Ltd Inspection apparatus and inspection method for semiconductor device

Also Published As

Publication number Publication date
JPS55125641A (en) 1980-09-27

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