JPS6137703B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information writing circuit for a semi-dynamic memory.

[Background of the invention]

Most semiconductor memories having memory cells based on flip-flop circuits distinguish between a read cycle and a write cycle of information based on whether or not a write command signal is received. That is, information is written into the memory cell only when a write command signal is received, and information is read from the memory cell during other periods. Therefore, if noise is added to the write command signal line during the read cycle period, it will cause malfunction. Particularly in the case of high-speed semiconductor memories, inversion of memory cells can occur with a short pulse width, so it is necessary to design a write circuit that is unlikely to cause malfunctions.

A conventional example of such a read/write circuit is disclosed in Japanese Patent Laid-Open No. 50-99052.

However, this technique does not give any consideration to preventing malfunctions.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that does not malfunction due to noise applied to a write command signal line.

[Summary of the invention]

In the present invention, a logical product of a write signal and a signal obtained by delaying the write signal is used as a write signal.

That is, in high-level writing, writing is performed only when both of the above-mentioned signals are at high level, and in low-level writing, both of the above-mentioned signals are written.This is made possible by taking the logical product of both signals.

[Embodiments of the invention]

FIG. 1 shows a block diagram of a semiconductor memory. In the memory cell matrix 10, a word line is selected by a word line input buffer circuit 11 and a word line drive circuit 12, which constitute a word line selection circuit, and a digit line input buffer circuit 13 and a digit line switching circuit, which constitute a digit line selection circuit. At 14, a digit line is selected and driven.

The digit line switching circuit 14 normally selects one digit line pair from among the digit line pairs in the memory cell matrix 10 in response to a signal from the digit line input buffer circuit 13. A read current is supplied to the selected digit line pair. At this time, one current of the digit line pair flows from the transistor of the memory cell selected by the word line, and the other current flows from the output circuit 15 via the digit line switching circuit 14. Which line of the digit line pair the current from the output circuit 15 flows through is determined by the information stored in the selected storage cell. In this way, the output circuit emits an output corresponding to the information stored in the selected memory cell, and the information is read out. On the other hand, in the write operation, an input pulse is applied to the write input buffer circuit 16 to set "1" information to the write drive circuit 1.
Either one of the "0" information write drive circuit 18 and "0" information write drive circuit 18 operates. Similarly, during reading, the digit line switching circuit causes current to flow through the selected pair of digit lines from the same current source as the read current, but one of the pairs is connected to the memory cell selected by the word line. Current flows from one transistor and the other from a digit switching circuit. The state of the memory cell at that time is fixed and writing is completed. Which of the selected pair of digit lines will cause current to flow from the memory cell is determined by
It is determined by which one of the "1" information write circuit 17 and the "0" information write circuit 18 is selected and driven by the output of the write information input buffer circuit 19. Chip select input buffer circuit 20 inhibits the operation of output circuit 15 and write drive circuits 17 and 18 in response to a chip select signal. According to the conventional method of directly adding the output of the write input buffer circuit 16 to the write drive circuits 17 and 18, the write input buffer circuit 1
When noise exceeding the threshold of 6 is added to the input, an output corresponding to the pulse width that causes the threshold is applied to the write drive circuits 17 and 18. Therefore, the write drive circuits 17 and 18 also operate, sending write drive signals due to noise to the cell matrix, causing malfunctions. The present invention provides a write input buffer circuit 1, as shown by a broken line 50 in FIG.
By ORing the input to 6 and its OR output, the write circuit is inhibited from operating in response to an input pulse whose pulse width is narrower than the delay time in the write input buffer circuit 16, and noise added to the write command line is suppressed. On the other hand, it becomes possible to obtain a more stable semiconductor memory.

FIG. 2 shows a method of configuring a write circuit among the circuits constituting the semiconductor memory shown in FIG. 1.

Terminal 21 is an input terminal for a write command signal, terminal 22 is an input terminal for a chip select signal, and terminal 23 is an input terminal for a write information signal.

Terminals 24 to 27 are reference voltage terminals corresponding to each input signal. A circuit mainly composed of transistors Q ₁ to _{Q 4} is a write input buffer circuit 16.
The circuit mainly composed of transistors Q ₅ to Q ₉ is the write drive circuit 17, 18,
Write drive signals are connected from terminals 28, 29 to the storage cell matrix.

An outline of the operation of this write drive circuit is as follows. During a write operation, a low voltage signal is applied to the write command signal input terminal 21. Since this voltage is lower than the voltage at terminal 24, transistor _Q2 of the write input buffer circuit conducts, and the base voltage of transistor _Q10 is driven to a low potential.

As a result, the base potential of transistor _Q5 becomes lower than the reference voltage at terminal 27, and the transistor
Q ₅ becomes non-conductive. Then, either transistor Q ₈ or Q ₉ becomes conductive in response to the write information signal at terminal 23, so when transistor Q ₅ becomes non-conductive, either transistor Q ₆ or Q ₇ becomes conductive in response to the write information signal. Then, a write drive signal is generated at the terminal 28 or 29. That is, the application of a signal lower than the reference voltage of the terminal 27 to the base of the transistor _Q5 becomes a criterion for determining whether or not the write drive circuit operates. Then, from the part explained above, the transistor from the second circuit diagram
In conventional write circuits except Q ₇₀ , terminal 21
When noise of a voltage lower than the reference voltage at the terminal 24 is added to the signal, the write input buffer circuit 16 is activated, and the signal is input to the write drive circuits 17 and 18 via the transistor _Q10 and the diode _D1 . When this input becomes lower potential than the reference voltage of terminal 27, terminals 28, 2
The output of the write circuit appears at 9. However, as in one embodiment of the present invention shown in FIG.
The write command signal applied to the write input buffer circuit 16 is ORed via the signal line 70 and the transistor 70, and the write drive circuit 1
7 and 18, even if noise with a pulse width narrower than the delay time in the write input buffer circuit is applied to terminal 21, the write drive circuit will not operate, and terminals 28 and 29 will have no noise. No effect appears.

This operation will be explained with reference to FIG.

In the conventional example, that is, when transistor Q ₇₀ is not used, the base voltage waveform of transistor Q ₅ is the third
As shown in FIG. 3B, the signal is delayed from the signal at the terminal 21 shown in FIG. 3A by the delay time td of the write input buffer circuit.

On the other hand, in the practical example of the present invention in which the output of the transistor Q ₇₀ is logically summed, the base voltage waveform of the transistor Q ₅ becomes a signal with a pulse width narrower by td than the input signal at the terminal 21, as shown in FIG. 3c. .
Furthermore, as shown by the broken line in FIG. 3, if the signal at the terminal 21 is an input signal whose width is narrower than td, the base voltage of the transistor _Q5 , that is, the write drive circuit does not operate. Therefore, according to the present invention, it is easy to realize a write circuit for a semiconductor memory that is unlikely to malfunction due to noise.

Output 60 is a signal for inactivating output circuit 15.

The above is a case where writing is performed when the write drive signal is at a low level, so we used logical sum to remove noise, but when writing is performed at high level, it is sufficient to use logical product. Of course.

This is because, as shown in FIG. 4, the relationship is opposite to that in FIG. 3. FIG. 4a shows the first write signal, and b shows its delayed signal.

As shown in FIG. 4, when writing is performed at a high level, c becomes high level and writing is performed only when both a and b become high level.

A signal shorter than the delay time td, such as the noise of code 1, does not appear in c at all by taking the logical product.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a semiconductor memory that is extremely effective in preventing malfunctions due to noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a method of configuring a semiconductor memory, FIG. 2 is a write circuit diagram showing a conventional method and an embodiment of the present invention, FIG. 3 is an operation waveform diagram of FIG. 2, and FIG. , is an operation waveform diagram when logical product is used in the case of high-level writing. 10...Memory cell matrix 11...Word line input buffer, 12...Word line drive circuit,
13...digit line input buffer, 14...digit line switching circuit.

Claims (1)

[Claims] 1. A write drive circuit for issuing an output as write information to a memory cell in accordance with write information from the outside, and a predetermined delay time for receiving a write command signal from the outside and operating the write drive circuit by its output. In the semiconductor memory having a write circuit including a write input buffer circuit having a write input buffer circuit, the write drive circuit performs a write operation when a first level signal is input, and the write command signal and the output of the write input buffer circuit are both It is characterized by comprising means for generating the signal at the first level only during the period when the signal is at the first level, and an output signal of the means for generating the signal is used as an input signal to the write drive circuit. semiconductor memory.