JPS592116B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information writing circuit for a semiconductor memory.

Most semiconductor memories having memory cells based on flip-flop circuits distinguish between a read cycle and a write cycle of information based on whether or not a write command signal is received. That is, information is written into the memory cell only when a write command signal is received, and information is read from the memory cell during other periods. For this reason, if noise is added to the write command signal line during the read cycle period, it can cause malfunctions.Especially in high-speed semiconductor memory, memory cells can be inverted with a short pulse width, so design a write circuit that is unlikely to cause malfunctions. Is required. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that does not malfunction due to noise applied to a write command signal line.

FIG. 1 shows a block diagram of a semiconductor memory.

The memory cell matrix 10 includes a word line input buffer circuit 11 and a word line drive circuit 1 that constitute a word line selection circuit.
2, a word line is selected, and a digit line input buffer circuit 13 and a digit line switching circuit 14, which constitute a digit line selection circuit, select and drive the digit line. Digit line switching circuit 14 normally selects one digit line pair from among the digit line pairs in memory cell matrix 10 in response to a signal from digit line input buffer circuit 13. A read current is supplied to the selected digit line pair. At this time, one current of the digit line pair flows from the transistor of the memory cell selected by the word line, and the other current flows from the output circuit 15 via the digit line switching circuit 14. Which line of the digit line pair the current from output circuit 15 flows through is determined by the information stored in the selected storage cell. In this way, the output circuit emits an output corresponding to the information stored in the selected memory cell, and the information is read out. On the other hand, a write operation is performed by applying an input pulse to the write input buffer circuit 16 and operating either the b information write drive circuit IT or the ``0'' information write drive circuit 18. The digit line switching circuit causes current to flow through the selected one of the digit line pairs from the same current source as the read current, as in the case of reading above, but one of the pairs is connected to the memory selected by the word line. One current flows from the transistor of the cell, and the other flows from the digit line switching circuit 〇 The state of the memory cell at that time is fixed and writing ends 0 Which of the pair of selected digit lines will the current flow from the memory cell? 6
1” information writing circuit 17, 60゛ information writing circuit 1
8, it is determined by which one is selected and driven by the output of the write information input buffer circuit 19.
The chip select input buffer circuit 20 outputs the output circuit 15 and the write drive circuit 1 in response to the chip select signal.
7 and 18 are prohibited. According to the conventional method in which the output of the write input buffer circuit 16 is directly applied to the write drive circuits 17 and 18, when noise exceeding the threshold of the write input buffer circuit 16 is added to the input, the pulse width corresponding to the threshold value is generated. Write the output, drive circuit 17,
It will be added to 18. Therefore, the write drive circuit 17
, 18 also operate, sending a write drive signal due to noise to the cell matrix, causing malfunction. The present invention
As shown by a broken line 50 in FIG. 1, by ORing the input to the write input buffer circuit 16 and its 0R output, writing is performed for an input pulse whose pulse width is narrower than the delay time in the write input buffer circuit 16. By inhibiting circuit operation, it is possible to obtain a semiconductor memory that is more stable against noise added to the write command line. FIG. 2 shows a method of configuring a write circuit among the circuits constituting the semiconductor memory shown in FIG. 1. Terminal 21 is an input terminal for a write command signal, terminal 22 is an input terminal for a chip select signal, and terminal 23 is an input terminal for a write information signal. Terminals 24 to 27 are reference voltage terminals corresponding to each input signal. A circuit mainly composed of transistors Q1 to Q4 is a write input cover J A circuit 16, and a circuit mainly composed of transistors Q, to Q is a write drive circuit (portions 17 and 18 in FIG. 1). and
The write drive signal is connected to the memory cell matrix from terminals 28 and 29.The operation of this write drive circuit is as follows. During a write operation, a low voltage signal is applied to the write command signal input terminal 21. Since this voltage is lower than the voltage at terminal 24, transistor Q2 of the write input buffer circuit becomes conductive, and the base voltage of transistor Q1 is driven to a low potential. As a result, the base potential of transistor Q5 becomes a potential lower than the reference voltage at terminal 27. Therefore, transistor Q5 becomes non-conductive. Then, in response to the write information signal of the terminal 23, the transistors Q8 and Q
, becomes conductive, so when transistor Q becomes non-conductive, either transistor Q6 or Q7 becomes conductive in response to the write information signal, and the terminal 28 or 29 becomes conductive.
A write drive signal is generated. That is, the application of a signal lower than the reference voltage of the terminal 27 to the base of the transistor Q5 becomes a criterion for determining whether or not the write drive circuit operates. In the part explained above, that is, in the conventional write circuit excluding the transistor Q7O from the second circuit diagram, when noise of a potential lower than the reference voltage of the terminal 24 is applied to the terminal 21, the write input buffer circuit 16 The data is operated, written through the transistor QlO and the diode D1, and input to the drive circuits 17 and 18. This input is terminal 2
When the potential becomes lower than the reference voltage 7, the output of the write circuit appears at terminals 28 and 29. However, as in the embodiment of the present invention shown in FIG. 2, the write command signal applied to the terminal 21 and the write input buffer circuit 16 are
0 and the transistor Q7O, and input the result to the write 1 drive circuits 17 and 18, the write drive circuit can operate even if noise with a pulse width narrower than the delay time in the write input buffer circuit is applied to the terminal 21. does not operate, and terminals 28 and 29 are not affected by noise. This operation will be explained with reference to FIG. In the conventional example, that is, when the transistor Q7O is not used, the base voltage waveform of the transistor Q5 changes as shown in FIG. 3a by the delay time Td in the write input cover circuit, as shown in FIG. 3b.
On the other hand, in the practical example of the present invention in which the output of transistor Q7O is logically summed, the base voltage waveform of transistor Q5 is delayed from the signal at terminal 21 as shown in FIG. 3c. The signal has a pulse width narrower than the input signal by Td. Furthermore, as shown by the broken line in FIG.
The drive circuit does not work.

Therefore, according to the present invention, it is easy to realize a write circuit for a semiconductor memory that is unlikely to malfunction due to noise. Output 60 is a signal for inactivating output circuit 15.

The above is a case where writing is performed when the write drive signal is at a low level, so we used logical sum to remove noise, but when writing is performed at high level, it is sufficient to use logical product. Of course.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a method of configuring a semiconductor memory, FIG. 2 is a write circuit diagram showing a conventional method and an embodiment of the present invention, and FIG. 3 is an operating waveform diagram of FIG.

Claims (1)

[Claims] 1 A write drive circuit for issuing an output according to external write information as write information to a memory cell, and a predetermined delay time for receiving an external write command signal and operating the write drive circuit by the output. In a semiconductor memory having a write circuit including a write input buffer circuit having a write input buffer circuit, a signal generated by ORing the write command signal and an output of the write input buffer circuit is input to the write drive circuit. A semiconductor memory characterized by being used as a signal.