JPS6137715B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides read-only memory (hereinafter referred to as ROM), programmable read-only memory (hereinafter referred to as ROM), and programmable read-only memory (hereinafter referred to as ROM).
The present invention relates to semiconductor memories such as PROM (hereinafter referred to as PROM) or erasable read-only memory (hereinafter referred to as EPROM).

An example of a conventional ROM is shown in Figure 1.
It consists of a MOS-FET (Metal Oxide Semiconductor Field Effect Transistor, hereinafter referred to as FET). The explanation will now be made assuming that each FET is an N channel. FET ₁ , which serves as a memory transistor, has a gate connected to word line 2, a source grounded, and a drain connected to bit line 3. Load FET ₄ is connected to bit line 3 at its source, and _its drain is connected to the power supply terminal (for example,
Vcc) and its gate is connected to the decoder line 5. A charge discharge FET ₆ is further connected to the bit line 3, and a constant voltage (for example, 1.6 to 1.8 V) is applied to the gate of the FET 6, so that the channel is inverted in a high resistance state.

In this ROM, a known method is used to store information, such as making the threshold voltage of FET ₁ smaller or larger than the power supply voltage of word line 2 depending on whether the information is "1" or "0". .
To read the information stored in FET ₁ , a selection signal is applied to decoder line 5 to turn FET ₄ on and supply power to bit line 3.
The voltage on the bit line 3 is stabilized at a suitable voltage value (for example, 3 to 3.5V) by the FET ₆ in a high resistance state.
When a selection signal is applied to the gate of memory transistor FET ₁ by the selected word line 2, and if "1" is stored in that FET ₁ , FET ₁ becomes conductive and the voltage of bit line 3 increases. decreases and the sense circuit detects "1", and conversely, when "0" is stored in FET ₁ , FET ₁
Since the bit line 3 remains in a non-conductive state, the voltage on the bit line 3 does not change and the sense circuit judges it as "0".

Next, when decoder line 5 becomes unselected,
FET 4 becomes non-conductive and stops supplying power to bit line 3. There is a stray capacitance 7 on the bit line 3, and when the decoder line 5 becomes unselected, the charge accumulated in this stray capacitance is
Gradually discharge through FET ₆ .

However, if the threshold value of charge discharge FET ₆ is manufactured to be higher due to process reasons, or if the voltage applied to the gate of FET ₆ is lowered, the resistance of FET ₆ may increase. , the discharge rate of the charge in the stray capacitance of the bit line ₃ decreases. In general, conventional semiconductor memory that relies only on FET ₆ for charge discharge takes time to discharge,
It has the disadvantage that access time is long.

An object of the present invention is to obtain a semiconductor memory with short access time by quickly discharging the charge accumulated in the stray capacitance of the bit line when the decoder line changes from the selected state to the non-selected state. The inverted signal of the decoder line signal that selects the bit line is input as the gate signal, and one electrode is grounded.
The above objective is achieved by connecting the FET to the bit line.

An embodiment of the present invention will be described below.

In Figure 2, for memory transistor
The structure and function of FET ₁ , load FET ₄ , and charge discharge FET ₆ are exactly the same as in the conventional ROM shown in FIG. 1, and a stray capacitance is similarly present in bit line 3. 10 is the same channel type as load FET ₄ (in this example, N channel type)
This FET has a gate connected to the decoder line 5 via an inverter 11, a drain connected to the bit line 3, and a source grounded.

In this embodiment, when a selection signal (high level signal) is applied to the decoder line 5, FET ₄ becomes conductive, but a low level signal is applied to the gate of FET ₁₀ via inverter 11.
Since FET ₁₀ remains non-conducting, it operates in the same way as the circuit of FIG. Next, when the signal on the decoder line 5 changes from the selection signal to the non-selection signal (low level signal), the load FET ₄ enters the non-conducting state and stops power supply to the bit line in 3, and the FET ₁₀ A high level signal is applied to the gate of the bit line 3 via the inverter 11 from the decoder line 5 to make the FET ₁₀ conductive, so that the charge stored in the stray capacitance 7 of the bit line 3 is not only discharged through the FET ₆ but also , is rapidly discharged through FET ₁₀ .

The operation of this embodiment will be compared with the conventional example shown in FIG. 1 based on the simulation results shown in FIG. 80ns
Assume that the decoder line 5 changes from a selected state to a non-selected state and the voltage level changes from a high level to a low level around (nanoseconds). In the case of Fig. 1, the charge accumulated in the stray capacitance of bit line 3 is
Since the bit line 3 is gradually discharged through the FET ₆ , the voltage on the bit line 3 also gradually decreases as shown by the broken line in FIG. 3, and if the detection level of the sense circuit is 2.0V, it is detected in about 300 ns. This is approximately the time it takes for bit line 3 to discharge the accumulated charge after decoder line 5 changes from the selected state to the unselected state.
This means that 220 ns (section A in Figure 3) is required. On the other hand, in the embodiment shown in FIG.
As the output voltage of the inverter 11 changes from a low level to a high level as the voltage changes from a high level to a low level, the accumulated charge on the bit line 3 increases.
It is rapidly discharged through FET ₁₀ , and bit line 3
As shown by the solid line in FIG. 3, the voltage decreases rapidly and is detected by the sense circuit around 1000 ns.
This means that in this embodiment, the discharge of the accumulated charge in bit line 3 only takes about 20 ns (section B in Figure 3), compared to about 220 ns in the conventional example.
This shows a time reduction of 200ns.

Using the circuit shown in Figure 1, the access time is approximately
While it requires 400 to 500 ns, when the circuit of this embodiment is used, it only takes about 200 to 300 ns, which is a time reduction of about 200 ns.

The above embodiments relate to ROMs configured with N-channel FETs, but P-channel FETs are also used.
It can also be constructed using FETs. Furthermore, the present invention is equally applicable to semiconductor memories such as PROM and FPROM.

As explained above, the present invention inputs the inverted signal of the signal of the decoder line that selects the bit line as the gate signal, and connects one electrode to the ground.
Since the FET is connected to the bit line, it is possible to achieve a semiconductor memory in which the charge stored in the bit line is discharged at a faster rate than in conventional semiconductor memories, and therefore has a shorter access time.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional semiconductor memory, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 compares the operation of the circuit in Fig. 1 and the circuit in the embodiment shown in Fig. 2. FIG. 3 is a diagram showing the voltage levels of each part for 1...Memory transistor FET, 2...Word line, 3...Bit line, 4, 6, 10
...FET, 5...Decoder line, 7...Stray capacitance, 11...Inverter.

Claims (1)

[Claims] 1 In a semiconductor memory in which a word line is connected to the gate of a memory transistor MOS-FET and a bit line selected by a decoder line is connected to one electrode, an inverted signal of the signal on the decoder line is input as a gate signal. A semiconductor memory characterized in that a MOS-FET whose electrode is grounded is connected to the bit line.