JPS6138511B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides a master CPU with main memory.
(central processing unit) and internal memory.
The present invention relates to a multiprocessor system consisting of a CPU and a slave CPU connected to it, the main memory of which can be directly accessed by the slave CPU.

In traditional multiprocessor systems, slave CPUs are connected to the system bus through a DMA (direct memory access) control circuit attached to the master CPU, and the DMA control circuit masters information about main memory addresses. It is received from the CPU and stored. And first, the slave CPU
outputs a DMA request signal to the DMA control circuit, and this
The slave CPU is configured to access the main memory under the control of the DMA control circuit. However, with this method, there are cases where the memory address to be accessed in main memory changes frequently,
When a large number of slave CPUs access the main memory, there is a problem in that processing power is significantly reduced.

In addition, the internal bus of the slave CPU can be
A method is sometimes used in which a slave CPU is directly connected to the bus and other slave CPUs are placed on standby while the slave CPU accesses the main memory, but with this method the processing speed is reduced by the amount of time the slave CPU waits. , Another drawback is that a CPU with a limited standby time cannot be used as a slave CPU.

This invention was made in view of the above circumstances, and an object of the present invention is to provide a multiprocessor system that can perform DMA transfer with main memory without reducing the processing ability of slave CPUs. do.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, a master CPU 1 and its main memory 2, which control the entire system, are connected to a plurality of slave CPUs 1, an address bus 3, a data bus 4, and control lines 5, 6, and 7, which constitute a system bus. tied together. Master
CPU 1 and main memory 2 are connected by a system bus. Each slave CPU 11 has an internal memory 12, and is interconnected by an address bus 13, a data bus 14, and a control line 15 that constitute an internal bus. These internal buses are connected to latch gate circuits 31, 32, 33, 3 of the DMA control circuit 22.
4, respectively, to the system bus. In this example, we use two slaves for convenience.
Although the CPU 11 is shown in the figure, it is assumed that an appropriate number of CPUs are provided. And these slaves
Numbers 1, 2, ...m, n (=m+1), ... on the CPU
It is expressed with ....

For each slave CPU11, the slave CPU
A decoder 21 is provided which receives 11 address signals as input. The address range of the internal memory 12 is preset in this decoder 21, and if the address input through the address bus 13 is included in this set address range, the decoder 21 sends an internal memory judgment signal of L level. is output, and this signal is sent to the internal memory 12 as a memory request signal. Also a slave
If the address output by the CPU 11 is outside the above set address range, the decoder 21 outputs an L-level DMA request determination signal. this
The DMA request determination signal is sent to the DMA control circuit 22. Therefore, the slave CPU 11 can read or write data from the internal memory 12 in a normal manner by outputting an address signal and a read or write control signal in the address range of the internal memory 12. Note that the address range of the main memory may be set in the decoder 21 instead of the address range of the internal memory.

When the slave CPU 11 writes or reads a decoder to or from the main memory 2, it outputs an address signal specifying the address of the main memory 2. Then, a DMA request determination signal is output from the decoder 21 and sent to the DMA control circuit 22, so that the DMA control circuit 22 performs DMA transfer control. The state of this DMA transfer is shown in FIG.

Now, when writing to the main memory 2 by DMA transfer, the slave CPU 11 outputs the address signal to the address bus 13, and also outputs the data signal to be written and the write control signal to the data bus 14 and the control signal. - Output to line 15. L level from decoder 21
When the DMA request determination signal is output, this signal is sent to the latch control terminals R of the latch gate circuits 31 and 34, so that the address signal and write control signal output from the slave CPU 11 are sent to the latch gate circuits 31 and 34. , 34. In addition, the signal is negative logic AND circuit 3
It is also sent to one input terminal of 6. Since a control signal, that is, an L-level write control signal is input to the other input terminal of the AND circuit 36, an L-level output is generated from the AND circuit 36, and this L-level signal triggers the latch of the latch circuit 32. Since it is input to control terminal R, slave CPU1
The data signal output from the latch gate circuit 32 is latched into the latch gate circuit 32.

The L level DMA request determination signal is a negative logic
It is also input to one input terminal of the AND circuit 25.
The set output Q of the flip-flop 24 is input to the other input terminal of the AND circuit 25. Since flip-flop 24 has been reset at this point, its set output Q is at L level. Therefore, the output of the AND circuit 25 becomes L level, and this L level signal is sent to the forced set input terminal S of the flip-flop 23, so that the flip-flop 23 is set. As a result, the set output Q of the flip-flop 23 becomes H level, and this H level signal is
It passes through the NOT circuit 29 and is sent to the master CPU 1 via line 6 as an L-level DMA request signal. Also, the set output Q of the flip-flop 23 is
It is also sent to the AND circuit 27 and the NAND circuit 30.

The DMA control circuit 22 is provided with a priority circuit. This priority circuit includes a flip-flop 23,
It consists of a NOT circuit 41, a NAND circuit 42, and a NAND circuit 30. In this example, slave CPU1
The priority order is higher in descending order of the numbers 1 to n attached to 1. Considering slave CPU11 with number m,
DMA prohibition signal DR (m-
1) is H level, this slave CPU1
DMA transfer by 1 is prohibited. That is, this H level signal is inverted by the NOT circuit 41 to become an L level signal, and this L level signal is
The signal is sent to the NAND circuit 30, and the gate of this NAND circuit 30 does not open. Also, since the L level signal of the NOT circuit 41 is input to the NAND circuit 42,
The output of the NAND circuit 42 is always at the H level, and serves as a signal DP _n that inhibits DMA transfer by the slave CPU 11 at the next stage. Furthermore, when the flip-flop 23 is set and a DMA request signal is output, the L level reset output of the flip-flop 23 is input to the NAND circuit 42,
Since the output of CPU 2 becomes H level, DMA transfer by the slave CPU 11 at the next stage with a lower priority is prohibited in this case as well.

When the DMA prohibition signal DP (m-1) is at the L level, DMA transfer by the slave CPU 11 with number m is possible. In this case, the output of the NOT circuit 41 becomes H level, and this H level signal becomes the NAND
input to circuit 30; This NAND circuit 30 also receives the H level set output Q of the flip-flop 23. Therefore, master CPU1
When the DMA request signal is received and a DMA permission signal at L level is output, this signal passes through the NOT circuit 28 and becomes an H level signal.
Enter 0. As a result, the output of the NAND circuit 30 becomes L level. Master CPU1 is slave
If the DMA request signal from the CPU 11 can be accepted, the above-mentioned L-level DMA permission signal is output, and the system bus is disconnected to enable DMA transfer.

The L level output signal of the NAND circuit 30 is sent to the gate control terminal G of the latch gate circuits 31 and 34, so these latch gate circuits 3
Gates 1 and 34 are opened, and the address signal and write control signal latched therein are sent to main memory 2 through address bus 3 and control bus 5. Also, NAND30 L
The level signal is sent to the negative logic AN circuit 35. The other input terminal of this AND circuit 35 has a latch.
Since the output signal of the gate circuit 34 is input,
When the L level write control signal is output from the latch/gate circuit 34, the output of the AND circuit 35 becomes L level, and this L level signal causes the latch/gate circuit 34 to output the L level write control signal.
Since the data signal is sent to the gate control terminal G of the gate circuit 32 and the gate is opened, the data signal latched in this circuit 32 is sent to the main memory 2. In this way, data output from the slave CPU 11 is written to a predetermined address in the main memory 2.

When the DMA transfer is completed and the DMA permission signal goes high, the output of the NAND circuit 30 also goes high, so this output is input to the clock input terminal T of the flip-flop 23. Since the data input terminal D of the flip-flop 23 is grounded, it is at L level. Therefore, flip-flop 23 is reset and its set output Q goes to L level, so the DMA request signal goes to H level. Since the reset output of this flip-flop 23 becomes H level, this H level signal is input to the NAND circuit 42 of the priority circuit, and at least this
The DMA inhibition of low priority circuits by the DMA control circuit is lifted.

After the slave CPU 11 outputs the address in the address range of the main memory 2, it has already transferred all the signals necessary for DMA transfer to the DMA control circuit 22, so this slave CPU 11
Processing can be performed independently of DMA transfer.

When the slave CPU 11 reads from the main memory 2 by DMA transfer, the slave CPU 11
The CPU 11 outputs an address signal specifying an address from which data in the main memory 2 is to be read to the address bus 13, and outputs an H level read signal R to the control line 15. Decoder 2
1 outputs the DMA request determination signal as described above, and this signal is sent to the latch gate circuit 3.
Since the address signal and read signal R are sent to the latch control terminals R of circuits 31 and 34,
are respectively latched. Further, the DMA request determination signal is inverted and input to one input terminal of the NAND circuit 37. Since the read signal R at H level is input to the other input terminal of this NAND circuit 37, a signal at L level is output from this circuit 37, and this output is applied to the gate control terminal G of the latch/gate circuit 33. Enter. This latch gate circuit 33 latches the data signal read from the main memory 2 and sent through the data bus 4 during DMA transfer, and it
The data signal read out when reading main memory 2 by DMA is latched. When an L level signal is output from the NAND circuit 37, the previous data signal latched in the latch/gate circuit 33 is output from this circuit 33. Since this data signal continues to be output until the current DMA transfer ends, the slave CPU 11 can take in this data signal at an appropriate timing.

The DMA inhibit signal from the previous circuit with high priority is at L level, and the signal from master CPU1 is at L level.
When a high level DMA permission signal is sent, the output of the NAND circuit 30 becomes L level, as described above. Then, the address signal and read signal R latched in the latch gates 31 and 34 are sent to the main memory 2. Further, the output of the NAND circuit 30 is inverted and inputted to one input terminal of the NAND circuit 38. Since the other input terminal of this NAND circuit 38 is connected to the output terminal of the latch gate circuit 34, the read signal R is inputted when the gate of this circuit 34 is opened. Therefore, the output of the NAND circuit 38 becomes L level, and this signal is sent to the latch control terminal R of the latch gate circuit 33, so that this circuit 33 latches the read data signal transferred from the main memory 2. It becomes wet,
The data read from the specified address of main memory 2 by DMA is latched when it is transferred through data bus 4. This latched data is taken in by the slave CPU 11 the next time it is read by DMA.

When the DMA transfer is completed and the DMA permission signal becomes H level, the flip-flop 23 is reset and the DMA prohibition for the lower priority circuit is released, as in the case of writing.

Figure 3 shows that the slave CPU 11 outputs an address signal included in the address range of the main memory 2.
After a DMA request determination signal is output and a DMA request signal is sent to master CPU 1 based on this signal, DMA is prohibited due to no DMA permission signal being output from master CPU 1 or by a circuit with a higher priority. This shows the situation when an address included in the address range of the main memory 2 is specified again from the slave CPU 11 before the output of the NAND circuit 30 becomes L level.

The data input terminal D of the flip-flop 24 has
The output of the AND circuit 27 is input. This AND
The set output Q of the flip-flop 23 and the output of the NAND circuit 30 are input to the circuit 27.
When flip-flop 23 is reset, or even if flip-flop 23 is set, when the output of NAND circuit 30 is at L level, the output of AND circuit 27 is at L level.
A DMA request determination signal is input to the clock input terminal T of the flip-flop 24 via a NOT circuit 26. Therefore, this flip-flop 24 is normally reset or kept in a reset state each time a DMA request determination signal is output, and the set output Q of the flip-flop 24 is
is at L level, and the reset output is at H level.

When the first DMA request determination signal is output, since flip-flop 23 has been reset at this point, flip-flop 24 is also reset. When the flip-flop 23 is set by the DMA request determination signal, one input terminal of the AND circuit 27 is connected to the flip-flop 23.
The set output Q of H level is inputted. and,
DMA is not permitted and the output of the NAND circuit 30 is high
If it is maintained at the H level, the other input of the AND circuit 27 is also at the H level, and the output of the AND circuit 27 is maintained at the H level.

When the second DMA request determination signal is output, this signal is input to the clock input terminal T of the flip-flop 24, so the flip-flop 24 is set. Therefore, the reset output becomes L level, and this L level signal is applied to the forced reset input terminal R of the flip-flop 23.
The flip-flop 22 is reset, and the H level signal is input to the interrupt input terminal of the slave CPU 11 and output to the slave CPU 1.
1 is interrupted. Therefore, this slave CPU 11 can determine DMA failure by accepting this interrupt and repeat the DMA transfer again.

As described above, according to this invention, the slave
Determine whether the address data output from the CPU is included in the main memory address range, and if it is included in the main memory address range
Since it is equipped with an address/data determination circuit that outputs a DMA request determination signal, when the slave CPU accesses the main memory, DMA transfer is possible by simply outputting the address of the main memory.
Also, when the above DMA request judgment signal is output, a DMA request signal is sent to the master CPU, and the slave
Depending on the necessary data output from the CPU
Equipped with a DMA control circuit that enables DMA transfer, this DMA control circuit includes address data.
A latch circuit stores the data necessary for DMA transfer, and when a DMA permission signal is received from the master CPU, the stored data is transferred to the main memory or slave.
A latch control circuit that sends signals to the CPU, and an interrupt that generates an interrupt signal to the slave CPU when the DMA request judgment signal is generated again after the DMA request signal is output but before the DMA permission signal is output from the master CPU. Since it includes a signal generation circuit, the slave
The CPU can perform the following processing regardless of DMA transfer, and the processing speed of the slave CPU can be increased. Furthermore, data transfer between main memory and slave CPU input/output devices requires
The time interval of DMA requests is determined by the processing time of the input/output device, but with this invention, it is possible to perform DMA transfer processing at a speed that matches the processing speed of the input/output device, and within this processing time. to DMA
If the transfer is not completed, an interrupt will occur, so try again.
DMA transfer processing can be repeated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of this invention.
FIGS. 2 and 3 are time charts showing the operation. 1...Master CPU, 2...Main memory, 11...
...Slave CPU, 21...Decoder, 22...
DMA control circuit, 23, 24... flip-flop, 31-34... latch gate circuit.

Claims (1)

[Claims] 1. In a multiprocessor system consisting of a master CPU with a main memory and a slave CPU with internal memory connected to the master CPU, the main memory can be accessed directly by the slave CPU. An address/data determination circuit that determines whether the address data output from the CPU is included in the address range of the main memory and outputs a DMA request determination signal if it is included in the address range of the main memory, and this DMA request. When the judgment signal is output, a DMA request signal is sent to the master CPU, and the necessary data output from the slave CPU enables DMA transfer.
This DMA control circuit includes a latch circuit that stores data necessary for DMA transfer including address data, and a latch circuit that stores data necessary for DMA transfer including address data.
A latch control circuit that sends the stored data to the main memory or slave CPU when a permission signal is received, and a latch control circuit that sends the stored data to the main memory or slave CPU when a permission signal is received;
When the DMA request determination signal is generated again before the DMA permission signal is output from the slave CPU,
and an interrupt generation circuit that generates an interrupt signal to.
Multiprocessor system. 2. A patent claim in which, when a plurality of slave CPUs are connected to a master CPU, the DMA control circuit is equipped with a priority circuit that controls the DMA permission signal from the master CPU according to a certain priority order. The multiprocessor system according to item 1.