JPS6138611B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to a high-density integrated circuit, preferably a MOS type integrated circuit.

By increasing the density of integrated circuits by reducing the size of each element, it is possible to improve electrical characteristics and improve productivity. However, since integrated circuits are manufactured through several types of photoresist processes, it is necessary to allow for a margin between each pattern. Although this margin can be reduced between patterns where self-aligned techniques are used, such as in conventional silicon gate technology,
No consideration is given to electrical insulation between the opening on the semiconductor surface and the electrode wiring that passes near the opening, and in conventional integrated circuit patterns, the electrode wiring of the first layer passes near the opening. Increase ineffective area.

An object of the invention is to provide a high density integrated circuit device.

A method for manufacturing an integrated circuit device according to the present invention includes a step of providing a first conductive wiring made of polycrystalline silicon on one main surface of a semiconductor substrate with a first insulating film interposed therebetween;
depositing a second insulating film on the first conductive wiring so that a part of the first conductive wiring is exposed;
a step of exposing a predetermined region of the semiconductor substrate and forming an opening with the exposed portion of the first conductive wiring serving as an opening end; and applying nitrogen or a nitrogen compound to the surface of the exposed portion of the first conductive wiring. The method is characterized by comprising a step of implanting ions to form silicon nitride, and a step of forming a second conductive wiring in contact with the predetermined region of the semiconductor substrate through the opening.

In the integrated circuit of the present invention, the first layer electrode wiring and the opening are self-aligned, and the second layer conductive wiring conductively coupled to the opening is insulated, so the effective pattern area ratio is high and the density is extremely high. High-speed operation can be obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a conventional MOS type integrated circuit, in which an active region pattern 11 in the first step is connected to a pair of first layer aluminum electrode wiring patterns 1 in the second step.
2, 12' intersect, and this wiring pattern 12, 1
An opening pattern 13 in the third step was provided in the insulating film on the active region between 2', and a second layer aluminum wiring 14 in the fourth step was formed through the opening pattern 13, which was conductively coupled to the active region and perpendicular to the first layer. It is something. For the chemical etching formation of the hole pattern 13, allowances a and a' are designed in consideration of the opening expansion during chemical etching and the alignment accuracy of each process in order to avoid electrical short circuit between the first and second layers. Therefore, in the conventional integrated circuit pattern, the first layer patterns 12, 12' make a large detour at the opening, which hinders high-density integration.

FIG. 2 shows a plan view of a reference example of the present invention, in which a pair of parallel first-layer aluminum electrode wiring patterns 2 in the second step are formed on the active region pattern 21 in the first step.
2, 22' intersect, and this wiring pattern 22, 2
An opening pattern 23 in the third step, which is self-aligned with the wiring pattern, is provided in the insulating film on the upper surface of the active region 21 between the holes 2'. Immediately below this opening pattern 23, there is a region of a conductivity type opposite to that of the reference silicon, and a second layer aluminum wiring 24 is conductively coupled to this region and extends orthogonally to the first layer.

3A to 3C are cross-sectional views showing the main manufacturing process of the reference example of FIG. 2. That is, in this reference example
In the active region 21 of the MOS type integrated circuit, N-type regions 32, 32', and 32'' are formed on one main surface of a P-type silicon 31.A 500 Å SiO ₂ layer is formed on the upper surface of the active region 21.
A first layer of aluminum wiring patterns 22, 22' is provided via films 33, 33'. A 0.5 μm SiO ₂ film 34 is deposited on these upper surfaces by vapor phase growth. In the opening pattern forming step, a photoresist film 35 is adhered to the upper surface of the SiO ₂ film 34, and an opening pattern 36 is obtained using a photomask. This pattern 36 is the wiring turn 2 of the first layer.
2, 22', the ends are treated with an acid-based etchant using the photoresist film 35 as a mask to form a vapor phase grown SiO ₂ film 34 and wiring pattern 2.
2, 22' on the upper surface of the opposite conductivity type region 32'.
The SiO ₂ film is removed. Next, as shown in FIG. 3B, using the photoresist film 35 as a mask, an anodization method is introduced to the sample, and the wiring patterns 22, 22' exposed in the opening pattern are made non-porous (barrier type) with a thickness of about 1000 Å. ) Alumina films 37, 37' are formed.
During this anodization step, a thin silicon oxide is also formed on the exposed portion of the opposite conductivity type region 32', but it is removed by performing pretreatment with an acid-based treatment liquid for the subsequent formation of the second conductive layer. The opening pattern 36' in this portion can be formed in self-alignment with the first layer wiring patterns 22, 22'. In addition, such anodic formation is usually carried out using a mixed solution of ammonium borate and ethylene glycol, and the alumina film 37, 3 of a predetermined thickness is formed through constant current formation and DC constant voltage formation at about 100V.
Get 7'.

Thereafter, as shown in FIG. 3C, the photoresist film with the openings formed therein is removed, and a second layer aluminum wiring pattern 24 is formed by photolithography. This wiring pattern 24 is conductively coupled to an N-type region 32' in the active region of the silicon 31 between the first layer aluminum electrode wiring patterns 22, 22', and is connected via the alumina films 37, 37' and the SiO ₂ film 34. Electrical insulation can be obtained from the underlying layer.

According to the above-mentioned example, since the first layer aluminum electrode wiring interval does not require a margin at the hole forming part,
A MOS type integrated circuit with high design density can be obtained. Such a high-density integrated circuit has a high operating speed and low power consumption, and can further reduce the decrease in productivity due to the occurrence of defects.

FIG. 4 shows a sectional view of an embodiment of the present invention.
This embodiment has an active region having an N-type region 42 and a 500 Å SiO ₂ gate insulating film 43 on the main surface of P-type silicon, and an inactive region protected by a thick SiO ₂ film 44 of about 1 μm. Gate insulating film 4
An electrode wiring 45 of polycrystalline silicon is adhered to the upper surface of 3, and the main portion is covered with a SiO ₂ film 46.
The second-layer aluminum electrode wiring 47 is led out from the N-type region 42 by conductive bonding to the exposed surface obtained by the opening pattern in which the opening ends reach the upper surfaces of the SiO ₂ film 44 and the first-layer electrode wiring 45. do. Electrical insulation with the electrode wiring 45 is achieved by implanting nitrogen or nitrogen compound ions into the polycrystalline silicon in the hole pattern area.
This is done by forming silicon nitride 48. Therefore, in this embodiment, the first layer of polycrystalline silicon electrode wiring 4
5 and the N obtained by self-alignment with the thick SiO ₂ film 44.
A second layer of aluminum wiring can be provided on the exposed surface of the mold region 42.

Also in the embodiment of FIG. 4 described above, the N-type region 4
Since the openings in 2 and the electrode wiring in the first layer are self-aligned, an integrated circuit with high pattern density and reduced additional capacitance of the wiring as the area of the N-type region is reduced, resulting in a faster operating speed. do.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an integrated circuit pattern of a conventional integrated circuit device. FIG. 2 is a plan view of a reference example of the present invention, and FIGS. 3A to 3C are cross-sectional views of the reference example of FIG. 2 during main manufacturing steps.
FIG. 4 is a sectional view of one embodiment of the present invention. In the figure, 11, 21...active region pattern, 1
2, 12', 22, 22'...first layer electrode wiring, 1
3, 23... Opening portion, 14, 24, 47... Second layer wiring, 31... P-type silicon, 32, 32',
32'', 42...N type region, 33, 33', 34,
46... SiO ₂ film, 35... Photoresist film,
36...Opening pattern, 37, 37'...Alumina film, 43...Gate insulating film, 44...Thick
SiO ₂ film, 45... Polycrystalline silicon electrode wiring, 4
8...Silicon nitride film.

Claims (1)

[Claims] 1. A step of providing a first conductive wiring made of polycrystalline silicon on one main surface of a semiconductor substrate via a first insulating film, and exposing a part of the first conductive wiring on the first conductive wiring. forming an opening in which a predetermined region of the semiconductor substrate is exposed and the exposed portion of the first conductive wiring serves as an opening end; a step of ion-implanting nitrogen or a nitrogen compound into the surface of the exposed portion of the first conductive wiring to form silicon nitride; and a second step of contacting the predetermined region of the semiconductor substrate through the opening.
1. A method of manufacturing an integrated circuit device, comprising the step of forming a conductive wiring.