JPS6138625B2 - - Google Patents

Description

[Detailed description of the invention]

(1) Field of Application of the Invention The present invention has high electron mobility and is used as a high-performance thin film transistor that can operate at room temperature.
(2) Conventional technology regarding the manufacturing method of InSb MIS structure If an MIS structure is made by forming an InSb film with a thickness of 0.03μ,
It is well known that MIS-FETs (MIS field effect transistors) that can operate at room temperature can be created (References: For example, FCLno and M.Epstein:
Proceeding of the IEEE, Vol.60No.8, page
997-999, 1972). The electron mobility _μH of InSb crystal is about 100 times higher than that of Si, Ge, GaAs, etc., so the transconductance Gm of MIS-FET becomes large and calculation operation can be performed in a low electric field (between source and drain). It is expected that ICs can be made. However, in reality, even though this comparison of μ _H is for bulk semiconductors, when the thickness of InSb is around 0.03 μm, the conventional bulk value (μ _H ≡60000 to 78000
cm ² /vs) much smaller than 1600-100cm ² /vs
The value could only be . (Electron mobility in the n-type inversion layer of SiMISFET is about 600 cm ² /vs.)
This was because an InSb film with near-perfect crystal properties could not be formed at this thickness, and the chances of electrons colliding with the crystal surface increased. From this, in order to increase _μH , the InSb film thickness should be increased, but if d is large, FET operation will not occur at room temperature. (Details will be explained later) Therefore, the InSb film thickness is
It had to be around 0.03 μm. Conventionally, the only method to form such a thin InSb film flatly is generally the vapor deposition method, but in terms of film properties, the manufacturing process has poor reproducibility, and the electron mobility of the film _μH exceeds 1600 cm ² /vs. It was not easy to obtain. Furthermore, in order to ensure operation as a MIS-FET, it is necessary to reduce the number of fixed charges in the film by reducing the surface state density to 10 ¹² cm ^-2 or less without causing hysteresis with the sweep of the gate voltage. A stable method for forming an insulating film has not yet been established. What has been tried so far as this insulating layer is a SiOx (x=1 to 2, usually referred to as SiO) film for the InSb vapor-deposited film. On the other hand, low temperature (−180℃~−273℃)
When forming an insulating layer on an InSb single crystal (thickness: 0.1 to 2 mm) for a MOS-FET that can operate at temperatures (°C), anodized InSb films and SiO ₂ films produced by glow discharge CVD are known. In general, these insulating film formation methods often cause gate hysteresis of 2V or more when FET is operated. That is, even when the gate voltage is the same, the value of the current flowing through the MIS transistor often differs when the gate voltage is increased and when it is decreased. Note that the process of heating the InSb film to 400°C or higher in this insulating film formation and electrode formation process is
It is necessary to note that all of these are unsuitable because they denature the InSb film (Reference: Japanese Patent Publication No. 1973-
17032). As mentioned above, the drawbacks of the conventional InSb-FET fabrication technology are (1) the inability to obtain a technology to increase the electron mobility _μH of the InSb film to 2000 cm ² /vs or more at a film thickness that causes MIS-FET operation; (2) It was not possible to form an InSb crystal film with a flat and uniform thickness using a method other than vapor deposition, and (3) the technology to obtain a gate insulating film layer that does not cause hysteresis has not been established. It happened to me. On the other hand, in FETs made of thin film semiconductors (generally referred to as TFTs) other than InSb, Si
Along with SOS technology, it was known that semiconductors could be removed by etching without any special effort to form an insulating layer for isolation between transistors. This has been considered to be an advantage in making it possible to arrange elements in a high density on a substrate when integrated circuits are manufactured.
However, in order to make ohmic contact when making electrode wiring, it is generally necessary to form a portion containing a high concentration of impurities in the semiconductor. Therefore, (4) if there is a diffusion heating process for introducing impurities, it is impossible to form the source/drain electrode spacing of MIS-FET to 1 μm or less, and it is impossible to reduce the distance between elements to 1 μm or less. It was possible. However, in the case of MIS-FET formation using thin film InSb, the only exception is the known technique of implanting H ⁺ ions to form a high concentration n ⁺ layer.
In this case, heating diffusion is unnecessary (Gypsum reference: Kodera et al., Physical Review B. Vol. 5, No.
8Page 3065-3078, April 1972). Conventional thin film transistors (TFT)
In addition to InSb, semiconductor films such as CdSe and CdS have been investigated. (Reference: Sasaki et al., Yamaguchi University Faculty of Engineering Research Report, Vol. 22, No. 2, 173 (1971)
and PK Weimer et al., RCA Review,
page661, December (1963)) These are room temperature
Unlike InSb, which exhibits intrinsic conduction, it exhibits extrinsic conduction. Therefore, in addition to the disadvantage that the mobility μ _H is originally smaller than that of InSb, grain boundaries and crystal defects significantly affect the electrical conduction characteristics.
It has been difficult to create high-speed operating transistors because the carrier is trapped by defects. However, it should be noted that InSb films, especially when subjected to zone melting, are suitable for room temperature transistors because the grain boundary potential does not significantly affect electrical conduction. (Reference: Kodera et al., Thin Solid Films, vol.36,
page483 (1976) and Shigeta et al., Journal of
Applied Physics, Vol.47, No.2, page621
(1976)). (3) Purpose of the Invention The present invention provides a method for manufacturing a device in which a plurality of InSb MIS structures can be created on one substrate by forming an InSb semiconductor thin film with high electron mobility and forming a stable gate oxide film. is to provide. (4) General explanation of the invention The requirement of the present invention is to enable MIS-FET operation.
InSb that can form a thin and flat InSb film with an electron mobility _μH of at least 2000cm ² /vs or higher.
A method for manufacturing the film, since μ _H decreases accordingly when the InSb film thickness is reduced, a method for creating an element structure that can perform MIS operation while increasing μ _H by doubling the thickness of the conventional film,
The present invention relates to a method for forming an insulating film that can reduce gate hysteresis compared to the above-mentioned InSb film. These solutions will be described below in order. Manufacturing method of high-mobility InSb thin film An InSb film is formed on a groove whose shape as seen from the surface is equal to the desired device shape and the depth is approximately 2 μm, and an InSb thin film device is obtained by zone melting and polishing. The method is publicly known (Reference: Kodera et al., Institute of Electronics and Communication Engineers material MR77-4, June 1977).
InSb with a thickness of 1.4 ± 0.05 μm on a 2-3 cm square substrate
In order to leave a film, it is also known to perform strain-free polishing using a gas ion sputtering method (ibid.). Due to zone melting, the crystal grains are coarse crystal grains measuring approximately 3 mm x 0.15 mm and elongated in the zone direction.
At this time, a high electron mobility μ _H (value at room temperature) of (6.0±0.3)×10 ⁴ cm ² /vsec was obtained with a thickness of 1.4 μm. 0.03~, which is thin enough to cause FET operation
To finish the InSb film uniformly to a thickness of 0.1μm,
Adjust the groove depth (0.1~2.0μ) so that the thickness after polishing on the soft metal lap is larger than the upper thickness range.
It is appropriate to set the thickness to about 1.5 m) and thin it to the desired thickness by a sputtering method using gas ions. Compared to other methods known up to now (e.g. vapor deposition only), a relatively thick InSb film (1 to 10 μm thick) as described above is zone melted.
Experiments conducted by the present inventors have revealed for the first time that it is easier to obtain a high electron mobility μ _H as shown in FIG. 1 by reducing the film thickness to 0.03 to 0.1 μm. In other words, compared to conventionally known methods, the present method reduces μ by more than twice as much as shown in Table 1.
_H is large. At this time, it is optional to chemically etch the surface with an appropriate etching solution to remove damage caused by the ions after sputter etching with gaseous ions.

[Table] (References: 1 Mizushima et al., Thin film physical properties engineering, Interface physical properties engineering, Ohmsha, 1968, p. 140, 2
M. Burvenich, Thin Solid Films, Vol27,
pages 129-134, 1957, 3 F, C, Epstein et al., proc, of IEEE, Vol, 60, No. 8, page 997
~999, 1972. ) Structure that increases _μH and allows MIS-FET operation: In an InSb crystal that exhibits intrinsic conduction at room temperature, the distance (depth) that an externally applied gate electric field can penetrate
is approximately given by the Debye distance l _p .
Since the carrier has an intrinsic concentration of 1.6×10 ¹⁶ cm ⁻³ , L _D is about 0.03 μm. Therefore, at room temperature
In order to operate as a FET, the InSb film thickness d must be calculated using the formula d
It is necessary to satisfy ≦0.03μm. (References: D,
R, Frankl, Electrical Properties of
Semiconductor Sunfaces, Pergamon, 1967,
(Page 23-27) However, as shown in FIG. 1, if d is small, _μH decreases and the operating characteristics (Gm and calculation speed) of the FET deteriorate, so it is preferable that d be large. Therefore, d should be 0.03 μm. However, the above example is for the case where the gate electrode is provided on one side, but if the gate electrode is provided on both the top and bottom surfaces of the InSb film, d can be twice that of the above example, allowing FET operation. At this time,
It is preferable to keep the two gates at a common potential. This idea allows the value of _μH to be set larger. Actually, even if d=0.10μm with this structure, MIS
It can function as a FET or MIS diode. Method of forming gate insulating film with low hysteresis:
Required conditions for the insulating film in MIS structure: Low fixed (polarized) charge inside the film. Semiconductor conductivity changes due to gate electric field. Slow states inside the film.
is small and does not cause hysteresis when sweeping the gate voltage. It has been known that in the case of an InSb anodic oxide film, when the capacitance C between the gate and the semiconductor is measured by varying the gate voltage V _G , hysteresis occurs in the range of 10 to 20 V, as shown in FIG. 2a. This figure shows the results of an experiment using our InSb single crystal, in which the above conditions were not satisfied. Instead, tetraethoxysilane (C ₂ H ₆ O) ₄ Si vapor and O ₂ gas (see Japanese Patent Publication No. 17032) using N ₂ gas as a carrier, and triisobutylaluminum vapor and O ₂ gas (see Japanese Patent Publication No. 17032) using Ar gas as a carrier. Sekiguchi et al., Easy-to-understand integrated circuits,
Sanpo, 1967, p. 141) and plasma.
Introduced into a CVD device (see above patent),
(SiO ₂ ) _{1-X (} Al ₂ O ₃ )
When formed on a single crystal to a thickness of 0.6 μm, hysteresis of 2 to 7 V frequently occurred, as shown in the dotted line sample (number #3) in FIG. 2b. For this reason, the present inventor formed a 0.6 μm thick (SiO ₂ ) _{1-X (} Al ₂ O ₃ ) Perform a heat treatment experiment at 100°C for at least 16 hours (preferably
Heat treatment for 20 hours) reduces this hysteresis to 0.05~
For the first time, we have found that it is effective in reducing the voltage to 0.4V (when the insulation film thickness is 0.6μm). At this time, no further improvement was observed even after 24 hours. The optimal heat treatment temperature is 100 to 200°C, and temperatures exceeding 300°C are inappropriate because the crystals will change in quality. 100℃,
C of InSb-MIS structure obtained by heat treatment for 22 hours
-V _G characteristics are shown as a solid line in Figure 2 b (sample number #4)
It was shown in Note that instead of this method, only SiO ₂ is deposited by glow discharge CVD method, and then Al ₂ O ₃ is deposited on top of it by laser evaporation method using CO ₂ laser at a substrate temperature of 200°C or less to form SiO ₂ / The Al ₂ O ₃ two-layer structure is optional. (See Tokugansho: 51-113097). Combining these methods to produce InSb films at room temperature
MIS-FET operation is possible, but details will be described in Examples. However, this MIS-FET is a semiconductor InSb
Since there are only two states in which there are many electrons (intrinsic carriers) in the film and there is a deficiency state, so-called complementary IC
cannot be formed. These MIS-FETs can also be used as MIS diodes, and a MIS-IC substrate can be obtained by combining a plurality of these on one substrate and forming electrode wiring. Figure 3 shows the cross-sectional structure of the MIS diode. Figure a shows an example in which the gate electrode 31 is formed on the upper part of the InSb film 35, and figure b shows an example in which the gate electrode 32 is formed in the lower part. Figure 4 shows the cross-sectional structure of MIS-FET. Figure a shows an example in which the gate electrode 41 is provided only on the top of the InSb film 45, and when the gate voltage V _G is 0 and it is in a conductive state (normally-ON), an n ⁺ layer 451 is formed for electrode formation. There's no need. But V
If _G is cut off (normally-OFF) when G is 0, H ⁺ ion is 200KeV
It is preferable to form the n ⁺ layer 451 by implanting 10 ¹⁵ dose/cm ² . At this time, heat treatment after implantation is not necessary. (Reference: Kodera et al., Physical Review,
B, Vol, 5, No. 8, pages 3065-3078). A structure to avoid this problem is shown in FIG. 2B, and in this case there is no need to form an n ⁺ layer. In a structure in which gate electrodes 41 and 42 are provided above and below the InSb film and the InSb film 45 is made thicker in order to increase _μH , the cross-sectional structure is as shown in FIG. In the MIS diode and MIS-FET illustrated above, even if the n ⁺ layer 451 for electrode is required, subsequent heat treatment is not required and the number of steps is reduced.
In the usage method that does not require the n ⁺ layer (normally-ON), the n ⁺ layer formation process (ion-
implantation) itself becomes unnecessary. In other words, since heat treatment is not required when forming electrodes, impurities can diffuse widely parallel to the film surface during the heat treatment process, creating small-area n ⁺ regions, especially in the case of thin films that contain grain boundaries, twins, and defects. It will be difficult to avoid the drawbacks. Therefore, according to the configuration of the present invention, it is possible to form an element electrode whose geometric dimensions are determined, so it can be said that the configuration is suitable for miniaturization of elements.
In addition, in order to separate and insulate each element on the IC,
There is no need for thermal diffusion, and the InSb thin film itself is separated by the buried structure from the beginning. therefore,
According to the present invention, elements can be miniaturized to the limit possible using photoetching technology, electron beam exposure technology, etc., and therefore the integration density of elements formed on one substrate can be increased. Since the gate area can also be reduced,
A feature of the present invention is that the gate capacitance Cox can be kept small and the semiconductor InSb having a large transconductance Gm is used, so that the IC operation speed evaluated by Gm/Cox can be designed to be large. In the configuration examples of the present invention shown in FIGS. 3 and 4, it is optional to divide the gate electrode to provide a plurality of gates. (5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. The target device structures are shown in FIG. 5, an MIS diode (plan view a) and an MIS-FET (plan view b). A cross section of the device structure taken along the line AA' in FIG. 2B is shown in FIG. This cross section is on the substrate side (InSb film
A FET having two gate electrodes 51 and 52 on the bottom side of the InSb film 55 and the top surface of the InSb film 55 is shown. gate 5
1 and 52 are connected in a direction not shown,
The current Isd between the source electrode 53 and the drain electrode 54 is controlled by this gate voltage V _G . InSb
Membrane 55 is embedded in glass 56, 57, 58. Glasses 56 and 58 were made of SiO ₂ , but glass 57 was made of silica glass (SiO ₂ ) _1-X (Al ₂ O ₃ )x containing alumina. Electrodes 51,5
3 and 54 are Al vapor deposited films. The gate electrode 52 is a Si gate in which a part of the high-resistance Si substrate is an n ⁺ layer. The manufacturing steps to obtain these structures will be sequentially described with reference to FIG. Diameter 25mm for IC substrate
A Si plate 60 (resistivity p = 100 Ωcm) with a diameter of 3 mm and a thickness of 3 mm was used. Impurities are introduced in advance into a portion of this 60 that is to become the Si gate 62. This is achieved by using the sputtered SiO ₂ film as a mask to diffuse phosphorus (P) (Figure 1). Next, sputter SiO ₂ 66 to a thickness of 0.5 μm and photo-etch it to form the desired FET.
SiO ₂ is removed to form a groove in a rectangular shape (FIG. 2). Next, attach the base glass 67 to x=0.18
(SiO _{21-X (} Al ₂ O ₃ )
This will be used as a base plate for InSb deposition (Figure 3). Subsequently, an InSb film 65 having a stoichiometric composition is deposited to a thickness of 6 μm from an In crucible and an Sb crucible using a known three-temperature deposition method. At this time, the substrate temperature was set at 330°C. Afterwards
0.15 μm of In651 was coated on this and 350 μm was applied in the atmosphere.
C. for 5 minutes to obtain a zone melt substrate (FIG. 4). Next, the InSb film is zone-melted in He gas containing a trace amount of O ₂ gas by the known hot wire zone melting method to coarsen the crystal grains and purify impurities (Japanese Patent Laid-Open No. 51-20682). When the InSb film thus obtained is polished on a Sn surface plate until the surface of the underlying glass 67 is exposed, it becomes 0.5 in thickness.
A μm-thick InSb film is obtained (Figure 5). after this,
InSb was produced using an ion milling device using Ar gas.
The film is combed to a thickness of 0.06 μm and the surface is etched by a small amount of 0.005 μm or less using a lactic acid/nitric acid mixture (Figure 6). The _μH of the InSb film having a thickness of about 0.06 μm thus obtained is 0.58×10 ⁴ cm ² /vsec. On the substrate having this InSb film, a 0.2 μm thick SiO ₂ film 68 was deposited by the claw discharge CVD method at a substrate temperature of 200° C. or lower.
(Figure 7). Thereafter, contact holes are formed on the SiO ₂ film 68 for the source and drain electrodes of the FET by photoetching (FIG. 8).
At this time, a contact hole for connecting the gate electrode that reaches the lower gate 62 is also formed by photoetching. Next, wiring electrode material 69
After coating approximately 0.01 μm of Cr as
-Refer to 34471) Deposit Al to a thickness of 0.8μm (Figure 9).
Next, by photo-etching again, Al is partially removed to form the source electrode 63 and drain electrode 6.
4. Form a gate electrode 61 (FIG. 10). At this time, the two gate electrodes 61 and 62 are coupled through a contact hole. After this, the MIS structure substrate obtained in this way was placed in the atmosphere at 100℃ and 20℃.
By applying heat treatment for several hours, we were able to stabilize the interface level between InSb and glass and achieve a hysteresis of 0.02V. The dimension of the MIS-FET created here has a source-drain distance of L = 5 μm,
The width of the InSb film is designed to be W=10 μm. InSb
Since the resistivity of the film was ρ=6.6×10 ^-2 Ωcm,
The element DC resistance at flat band is Rsd = 5.5K
It is Ω. Generally, the transconductance Gm (in the triode operating region), where C is the gate-source capacitance with respect to the source-drain electric field Ed, is given by Gm=C/L×μ _H ×Ed. From now on, the calculation speed index Gm/C
is Gm/C=μ _H Ed/L. μ _H =0.58×10 ⁴ cm ² /vs, Ed=2×10 ² v/
cm, for L=5μm, Gm/C=2.3×
10 ¹⁰ sec ^-1 = (0.043nsec) ^-1 is obtained. At this time, the source-drain voltage LEd is 0.10V, which proves that it is in the above-described three-electrode operation region (because it is sufficiently smaller than the gate voltage). When the value of the parameter Gm/C mentioned above is calculated in the case of an n-channel Si-MIS-FET in the triode or pentode operating region, μ _H = 600 cm ² /vsec, E _D =
10 ⁴ v/cm, so for L=5μm
Gm/C=1.2×10 ¹⁰ sec ⁻¹ =(0.083 nsec ⁻¹ ) ⁻¹ . In other words, InSb-MIS-FET can perform calculations about twice as fast. In actual Si-MOS-IC, the calculation time per transistor is 1 to 0.3 nsec, as mentioned above.
It is longer than 0.083 nsec, but this is because the capacitance of electrodes and wiring is not taken into account. InSb―MIS―
Assuming an IC, the capacitance of the electrode wiring can be reduced by eliminating the need for isolation between elements, so it is easy to design the calculation time to about 0.1 nsec when using an IC. (6) Summary As explained above, according to the present invention, an InSb thin film exhibiting a value of μ _H = 2-8×10 ³ cm ² /vsec, which could not be achieved conventionally, can be made to a thickness of 0.03 that allows MIS-FET operation.
This is the first InSb film suitable for high-speed arithmetic circuits, as it can actually be produced with a thickness of ~0.1 μm, and while conventional gate hysteresis could not be suppressed, this can be reduced to a value sufficient for MIS-FET operation. It became possible to design MIS-FET. Since this FET-based IC has shown the possibility of faster calculation speed than the conventionally widely used Si-FET-IC, we believe that the present invention can make a sufficient contribution to industry.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the relationship between the film thickness d and electron mobility of an InSb thin film produced by the manufacturing method of the present invention, and Figure 2 is a diagram showing the relationship between gate voltage and capacitance of an anodic oxide film and an insulating film produced by the plasma CVD method of the present invention. Figure 3 is a configuration example of an MIS diode (cross-sectional view), Figure 4 is a configuration example of an MIS-FET (cross-sectional view),
FIG. 5 shows a specific example (plan view and cross-sectional view) of an MIS diode and FET, and FIG. 6 shows a cross-sectional view of each step of the specific manufacturing method.

Claims (1)

[Claims] 1. A groove having a depth of 0.1 to 2.0 μm and a planar shape of a desired device shape is provided on a conductive gate formed by introducing impurities into a substrate,
Moreover, after depositing an InSb semiconductor film on the structure _whose groove surface is composed of (SiO _{2 ) 0.82} (Al ₂ O ₃ ) _0.18 and performing microzone melting, The structure is polished on a soft metal lap to leave the InSb semiconductor film only in the groove, and then this
After the InSb film is thinned by a sputtering method using gas ions to uniformly reduce its thickness to 0.03 to 0.1 μm, a gate insulating film made of SiO ₂ is formed at least on the surface of the InSb film, and a conductive gate is placed on top of it. After forming a layer, the MIS structure is further heated in the atmosphere for 100~
A method for manufacturing an InSbMIS structure, characterized by heat treatment at a temperature of 200°C for 16 to 24 hours.