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JPS6138634B2 - - Google Patents
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JPS6138634B2 - - Google Patents

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Publication number
JPS6138634B2
JPS6138634B2 JP8843078A JP8843078A JPS6138634B2 JP S6138634 B2 JPS6138634 B2 JP S6138634B2 JP 8843078 A JP8843078 A JP 8843078A JP 8843078 A JP8843078 A JP 8843078A JP S6138634 B2 JPS6138634 B2 JP S6138634B2
Authority
JP
Japan
Prior art keywords
electrode
layer
semiconductor chip
wiring layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8843078A
Other languages
Japanese (ja)
Other versions
JPS5516415A (en
Inventor
Masao Meguro
Tsunetoshi Kawabata
Hiroyuki Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8843078A priority Critical patent/JPS5516415A/en
Publication of JPS5516415A publication Critical patent/JPS5516415A/en
Publication of JPS6138634B2 publication Critical patent/JPS6138634B2/ja
Granted legal-status Critical Current

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  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置例えば発光ダイオードに関
するものである 発光ダイオードとしGaAlAs等の半導体基板の
表面にpn接合を形成した半導体チツプを第2図
a,bに示すようなシリコン基板1上に絶縁層2
を介して配線層3,4を形成してなる配線基板に
フエイスダウンボンデイングした構造で、pn接
合に順方向電流を流すことによつて光を発生さ
せ、半導体チツプの裏面に向つて照射した光を信
号として使用するようにしたものがある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, for example, a light emitting diode. A semiconductor chip having a pn junction formed on the surface of a semiconductor substrate such as GaAlAs as a light emitting diode is used as a silicon substrate as shown in FIGS. 2a and 2b. Insulating layer 2 on top of 1
This structure is face-down bonded to a wiring board with wiring layers 3 and 4 formed through the pn junction, and light is generated by passing a forward current through the pn junction, and the light is irradiated toward the back side of the semiconductor chip. There are some that use it as a signal.

このような発光ダイオードの半導体チツプは一
般に表面中央部にダイオードの一極を成す円形状
電極を、その周辺部に他の極を成すリング状電極
を配置した電極構造をとる。したがつて、配線基
板も第2図aに示すように中央部に半導体チツプ
の円形状電極と対応する円形状配線層3を、その
周辺部にリング状電極と対応するリング状配線層
4を配置した構造をもつ。そして、リング状配線
層4の一部には欠格部5を設け、該部に中央の円
形状配線層3とそのターミナル部3aとを結ぶ配
線層3bを通している。もちろん、この場合半導
体チツプのリング状電極にも配線層の欠格部5に
対応して欠格部が設けられていりる。そして、半
導体チツプの表面を配線基板の表面に対向させ、
X,Y方向の位置合せのみならず半導体チツプの
リング状電極における欠格部と配線基板のリング
状配線層における欠格部とが対応するように回転
方向(θ方向)の位置合せをした状態でフエイス
ダウンボンデイングが行なわれる。ところで、半
導体チツプの位置合せはX,Y方向についてはさ
ほど困難ではないが、チツプ形状が半球状でかつ
ボンデイング面が下向きであるのでθ方向につい
ては極めて困難であつた。そのためθ方向の位置
ずれよつて電極間が短絡するという不良が比較的
多かつた。
A semiconductor chip for such a light emitting diode generally has an electrode structure in which a circular electrode forming one pole of the diode is arranged at the center of the surface, and a ring-shaped electrode forming the other pole is arranged at the periphery. Therefore, as shown in FIG. 2a, the wiring board also has a circular wiring layer 3 in the central part corresponding to the circular electrode of the semiconductor chip, and a ring-shaped wiring layer 4 corresponding to the ring-shaped electrode in the peripheral part. It has an arranged structure. A disqualified part 5 is provided in a part of the ring-shaped wiring layer 4, and a wiring layer 3b connecting the central circular wiring layer 3 and its terminal part 3a is passed through the disqualified part 5. Of course, in this case, the ring-shaped electrode of the semiconductor chip is also provided with a disqualified part corresponding to the disqualified part 5 of the wiring layer. Then, the surface of the semiconductor chip is opposed to the surface of the wiring board,
The face is aligned not only in the X and Y directions, but also in the rotational direction (θ direction) so that the defective part in the ring-shaped electrode of the semiconductor chip corresponds to the defective part in the ring-shaped wiring layer of the wiring board. Down bonding is performed. By the way, alignment of the semiconductor chip is not so difficult in the X and Y directions, but it is extremely difficult in the θ direction because the chip is hemispherical and the bonding surface faces downward. Therefore, defects such as short circuit between electrodes due to positional deviation in the θ direction were relatively common.

本発明はこのような問題を解決すべくなされた
もので、半導体チツプのフエイスダウンボンデイ
ングにあたつてθ方向の位置合せが不要となる半
導体装置を提供することを目的とするものであ
る。
The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device that does not require alignment in the θ direction during face-down bonding of semiconductor chips.

上記目的を達成するための本発明の一実施態様
は、半導体表面における中央部にダイオードの一
極を成す円形状電極(第1電極)を有し、それを
囲む位置にダイオードの他を極なすリング状電極
(第2電極)を有する半導体チツプと、その中央
部表面に上記円形状電極に対応する円形状第2配
線層(第1導体層)を有し、それを囲む位置の表
面に上記リング状電極と対応するリング状第2層
配線層(第2導体)を有し、上記円形状第2配線
層は、上記リング状第2層配線層と層間絶縁膜を
介して交差(クロス)し、上記リング状第2層配
線層の外側主面に引出されてなる多層配線基板と
を、相互に対向させて電極間接続してなることを
特徴とするものである。
One embodiment of the present invention for achieving the above object has a circular electrode (first electrode) that forms one pole of a diode at the center of the semiconductor surface, and a circular electrode that forms the other pole of the diode at a position surrounding it. A semiconductor chip having a ring-shaped electrode (second electrode), a circular second wiring layer (first conductor layer) corresponding to the circular electrode on the central surface thereof, and the above-mentioned wiring layer on the surface surrounding the semiconductor chip. It has a ring-shaped second wiring layer (second conductor) corresponding to the ring-shaped electrode, and the circular second wiring layer crosses the ring-shaped second wiring layer via an interlayer insulating film. The multilayer wiring board drawn out from the outer main surface of the ring-shaped second wiring layer is arranged to face each other and connected between the electrodes.

以下本発明を実施例により説明する。第1図
a,bは本発明の一実施例に係る発光ダイオード
を示すもので、aが配線基板の平面図、bが配線
基板に半導体チツプを取り付けた状態におけるA
―A視断面図である。
The present invention will be explained below with reference to Examples. Figures 1a and 1b show a light emitting diode according to an embodiment of the present invention, in which a is a plan view of a wiring board, and b is a diagram showing a state in which a semiconductor chip is attached to the wiring board.
-A sectional view.

1はシリコン基板、2はシリコン基板1上に全
面的に形成されたシリコン酸化物(sio2)膜、6
はカソード電極を成す6bはアノード電極を成す
第1層配線層、7は層間絶縁体(例えばポリイミ
ド樹脂)層、8はカソード電極を成す8bはアノ
ード電極を成す第2配線層、8cは第1層配線層
3と第2層配線層(第1導体層)8との間のスル
ーホール(破線による斜線部分)、9はアノード
電極を成すリング状配線層(第2導体層)で、層
間絶縁体層7を介してカソード電極を成す第1層
配線層6aとアノード電極を成す第1層配線6b
とクロスしている。9aはそのターミナル、10
は発光ダイオードチツプ、11aはp型層、12
はp+型層、13はn型層、14はp―n接合を
保護するために形成した絶縁膜である。15は円
形状のカソード電極(第1電極)、16はカソー
ド電極15を取り囲むように形成された部分的欠
格部を有しないリング状アノード電極(第2電
極)である。半導体チツプ10の電極15,16
と配線基板の配線層8,9とを相互に接続するた
めには、熱圧着法による、フエイスダウンボンデ
イングで、半導体チツプと配線基板とを対向さ
せ、単にX,Y方向の位置合せをした状態で行
う。
1 is a silicon substrate; 2 is a silicon oxide (SIO 2 ) film formed entirely on the silicon substrate 1; 6
6b constitutes a cathode electrode, 6b is a first wiring layer that constitutes an anode electrode, 7 is an interlayer insulating layer (for example, polyimide resin), 8 is a cathode electrode, 8b is a second wiring layer that is an anode electrode, and 8c is a first wiring layer. A through hole (shaded portion by broken line) between the layer wiring layer 3 and the second layer wiring layer (first conductor layer) 8, 9 is a ring-shaped wiring layer (second conductor layer) forming an anode electrode, and interlayer insulation A first layer wiring layer 6a forming a cathode electrode and a first layer wiring layer 6b forming an anode electrode via the body layer 7
It crosses with. 9a is the terminal, 10
is a light emitting diode chip, 11a is a p-type layer, 12
13 is a p + type layer, 13 is an n type layer, and 14 is an insulating film formed to protect the pn junction. Reference numeral 15 indicates a circular cathode electrode (first electrode), and reference numeral 16 indicates a ring-shaped anode electrode (second electrode) having no partial defects formed so as to surround the cathode electrode 15. Electrodes 15 and 16 of semiconductor chip 10
In order to mutually connect the wiring layers 8 and 9 of the wiring board, the semiconductor chip and the wiring board are faced to each other by face-down bonding using thermocompression bonding, and the semiconductor chip and the wiring board are simply aligned in the X and Y directions. Do it with

このような本発明によれば、配線基板を多層配
線構造にし、内側電極の引出しをリング状の外側
電極と絶縁膜を介してクロスする下層配線を介し
て行うので、リング状電極には内側電極の引出し
のための欠格部を設けることが不要であり、半導
体チツプの回転角θに位置合せをすることなくフ
エイスダウンボンデイングしても両極間がシヨー
トしなくなる。単にX,Y方向の位置合せのみで
支障なくフエイスダウンボンデイングすることが
できる。したがつて、発光ダイオードの組立工数
が低減され、自動化も容易となる。
According to the present invention, the wiring board has a multilayer wiring structure, and the inner electrode is drawn out via the lower layer wiring that crosses the ring-shaped outer electrode via the insulating film. It is not necessary to provide a disqualified portion for drawing out the semiconductor chip, and even if face-down bonding is performed without alignment to the rotation angle θ of the semiconductor chip, the distance between the two poles will not be shot. Face-down bonding can be performed without any problem simply by positioning in the X and Y directions. Therefore, the number of man-hours required for assembling the light emitting diode is reduced and automation becomes easy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a,bは本発明の一実施例を説明するた
めのもので、aが発光ダイオード用配線基板の平
面図、bが配線基板に半導体チツプをフエイスダ
ウンボンデイングした状態におけるA―A視縦断
面図である。第2図a,bは従来例を説明するた
めのもので、aが配線基板の平面図、bがA―A
視縦断面図である。 1……シリコン基板、2……sio2膜、3……円
形配線層、4……リング状配線層、5……欠格
部、6a……第1層配線層(カソード側)、7,
6b……第1層配線層(アノード側)、7……層
間絶縁体層、8……第2層配線層(カソード
側)、8c……スルーホール、9……リング状配
線層(アノード側)、10……発光ダイオードチ
ツプ、11……p層、12……p+層、13……
n/n+層、14……絶縁膜、15……カソード
電極、16……アノード電極。
Figures 1a and 1b are for explaining one embodiment of the present invention, in which a is a plan view of a wiring board for a light emitting diode, and b is an A-A view of a semiconductor chip face-down bonded to the wiring board. FIG. Figures 2 a and b are for explaining the conventional example, where a is a plan view of the wiring board and b is A-A.
FIG. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... SIO 2 film, 3... Circular wiring layer, 4... Ring-shaped wiring layer, 5... Disqualified part, 6a... First layer wiring layer (cathode side), 7,
6b...First wiring layer (anode side), 7...Interlayer insulator layer, 8...Second wiring layer (cathode side), 8c...Through hole, 9...Ring-shaped wiring layer (anode side) ), 10...Light emitting diode chip, 11...p layer, 12...p + layer, 13...
n/n + layer, 14... insulating film, 15... cathode electrode, 16... anode electrode.

Claims (1)

【特許請求の範囲】 1 (a) 異なる導電型の半導体を接合してなるダ
イオードを有する半導体チツプと、 (b) 該半導体チツプ表面の一部に設けられ、前記
ダイオードの一極を成す第1電極と、 (c) 前記半導体チツプ表面に前記第1電極を囲む
如く配置されてなる前記ダイオードの他極を成
す第2電極と、 (d) その主面一部において、前記第1電極に対応
して設けられた第1導体層と、前記第2電極に
対応して設けられ、その第1導体層を取り囲む
第2導体層とを有し、かかつ前記第1導体層は
絶縁膜を介して第2電極に対してクロスし前記
第2導体層の外側主面部分へ引出されてなる配
線基板と、 を具備し、前記第1電極と第1導体層とをおよび
前記第2電極と第2導体層とをそれぞれ接続して
なることを特徴とする半導体装置。
[Claims] 1. (a) A semiconductor chip having a diode formed by joining semiconductors of different conductivity types; (b) A first semiconductor chip provided on a part of the surface of the semiconductor chip and forming one pole of the diode. (c) a second electrode forming the other electrode of the diode, which is arranged on the surface of the semiconductor chip so as to surround the first electrode; (d) a part of the main surface thereof corresponds to the first electrode; and a second conductor layer provided corresponding to the second electrode and surrounding the first conductor layer. a wiring board that crosses the second electrode and extends to the outer main surface portion of the second conductor layer; A semiconductor device comprising two conductor layers connected to each other.
JP8843078A 1978-07-21 1978-07-21 Diode Granted JPS5516415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8843078A JPS5516415A (en) 1978-07-21 1978-07-21 Diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8843078A JPS5516415A (en) 1978-07-21 1978-07-21 Diode

Publications (2)

Publication Number Publication Date
JPS5516415A JPS5516415A (en) 1980-02-05
JPS6138634B2 true JPS6138634B2 (en) 1986-08-30

Family

ID=13942562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8843078A Granted JPS5516415A (en) 1978-07-21 1978-07-21 Diode

Country Status (1)

Country Link
JP (1) JPS5516415A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10255932A1 (en) 2002-11-29 2004-06-17 Osram Opto Semiconductors Gmbh Optoelectronic component
JP4317697B2 (en) * 2003-01-30 2009-08-19 パナソニック株式会社 Optical semiconductor bare chip, printed wiring board, lighting unit, and lighting device
JP5612991B2 (en) 2010-09-30 2014-10-22 シャープ株式会社 LIGHT EMITTING DEVICE AND LIGHTING DEVICE HAVING THE SAME
JP6379542B2 (en) * 2014-03-14 2018-08-29 日亜化学工業株式会社 Lighting device
JP2014187392A (en) * 2014-06-23 2014-10-02 Sharp Corp Light-emitting device and luminaire having the same

Also Published As

Publication number Publication date
JPS5516415A (en) 1980-02-05

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