JPS6138660B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit, and more particularly to a receiving circuit that is used for multiplex control of loads by power line transmission or the like and is controlled by control signals transmitted via a power line.

Conventionally, in this type of receiving circuit, as shown in FIG. 4, a series circuit consisting of a coupler 8' and a limit circuit 9' is connected to the power line 4, and the output end of the limit circuit 9' is connected to a capacitor _C1. ′ and a diode D ₁ ′ are connected to the base of a transistor Q ₁ ′ whose emitter is grounded, and
The collector of Q ₁ ' is connected to the output terminal of a rectifier circuit 14' which is connected to the power line 4 through a resistor R ₁ ', and a resistor
_R2 ' to one input terminal of the NOR circuit NOR', and the other input terminal of the NOR circuit NOR' is connected to a resistor.
It is connected to the output terminal of the gate pulse generation circuit 11' which is connected to the power line 4' via R ₃ ', and in addition, the output terminal of the NOR circuit NOR' is connected to the two-stage flip-flop FF ₁ ', FF. Since it was connected to the gate of the SCR Q ₂ ' via the SCR Q ₂ ', the configuration was complicated, and furthermore, it was difficult to downsize and reduce costs. The present invention seeks to provide a receiving circuit which eliminates the above-mentioned drawbacks.

The receiving circuit of the present invention will be explained below with reference to the drawings.

In Figures 1 and 2, 1 is a receiving circuit;
It is connected via a block filter 2 to a power line 4 connected to a commercial power source 3. Reference numeral 5 denotes a transmitting circuit connected to the power line 4, which transmits a control signal _S3 to the receiving circuit 1 via the power line 4 in response to the press of the control switch 6, and transmits the control signal S3 to the receiving circuit 1 via the receiving circuit 1, and transmits the control signal S3 to the receiving circuit 1, which transmits a load 7 such as a lamp. drive.

Reference numeral 8 denotes a coupler connected to the power line, which applies a predetermined control signal _S3 transmitted from the transmitting circuit 5 via the power line 4 to one input end of the received signal detection circuit 10 via the limit circuit 9. . 11 is a gate pulse generation circuit connected to the power line 4;
The gate pulse _S2 that rises at phase O and falls at phase π of power supply voltage _S1 is applied to the received signal detection circuit 1.
0 to the other input terminal. 12 is a relay drive circuit, which connects the received signal detection circuit 10 and the relay circuit 1;
3, and drives the relay circuit 13 in response to the arrival of the control signal _S3 , thereby operating the load 7 appropriately. 14 is a rectifier circuit connected to the power line 4, the output end of which is connected to the received signal detection circuit 10 and the gate pulse generation circuit 1.
1. Connected to relay drive circuit 12 and relay circuit 13.

In more detail, both ends of the power line 4 (one of the two is grounded) via the capacitor C ₁
is connected to the capacitor, and one end of the secondary winding is connected to the capacitor.
It is grounded through C ₂ and the other end is directly grounded. _G1 is an inverter of the limit circuit 9, the input end of which is connected to the intermediate tap of the secondary winding of the transformer IR through a series circuit of resistor _R1 and capacitor _C3 , and the input end is connected to the intermediate tap of the secondary winding of the transformer IR. Resistance R between ₂
is inserted. NOR is received signal detection circuit 1
0 NOR circuit, one input end of which is connected to the output end of the inverter _G1 of the limit circuit 9 through a series circuit of the first and second resistors _R3 , _R4 and the diode _D1 . . _R5 is a resistor of the gate pulse generation circuit 11, one end of which is connected to the non-grounded side of the power line 4, and the other end of which is grounded via a resistor _R6 . _G2 is an inverter, whose input end is connected to the connection point of the low resistors _R5 and _R6 via a resistor _R7 , and whose output end is connected to the input end of the inverter _G3 .
SW ₁ is a switch, one fixed contact is connected to the output end of the inverter G ₂ , the other fixed contact is connected to the output end of the inverter G ₃ , and the movable contact is connected to the capacitor C ₄ and the third resistor R. It is connected to the other input terminal of the NOR circuit NOR through a series circuit with ₈ . D ₂ and D ₃ are diodes of the rectifier circuit 14, which are connected in series with each other via a resistor R ₉ and inserted between the non-grounded side of the power line 4 and the collector of the transistor Q ₁ of the relay drive circuit 12. There is. ZD is a Zener diode, which is inserted between the diode _D3 and the ground. _C5 is a capacitor connected in parallel to the Zener diode ZD. _R10 is a resistor, one end of which is connected to the connection point between the diode _D3 and the Zener diode ZD, and the other end connected to the connection point of the diode _D3 and the Zener diode ZD.
is connected to the connection point with resistor R ₈ . _R11 is a fourth resistor, one end of which is connected to the connection point between the diode _D3 and the Zener diode ZD,
The other end is connected to the connection point between the first and second resistors R ₃ and R ₄ . _C6 is a first capacitor connected in parallel to the fourth resistor _R11 . _Q1 is a transistor of the relay drive circuit 12, the collector is connected to the connection point between the diode _D3 and the Zener diode ZD of the rectifier circuit 14, the base is connected to the output terminal of the NOR circuit NOR of the received signal detection circuit 10,
The emitter is the fifth resistor R ₁₂ and the second capacitor C ₇
is grounded through a series circuit with. _Q2 is
In the SCR, the anode is connected to the connection point between the diode _D2 and the resistor _R9 of the rectifier circuit 14 through the relay coil Ry of the relay circuit 13, and the gate is connected to the fifth resistor through the sixth resistor _R13 . R ₁₂ and the second capacitor C ₇ are connected to the connection point, and the cathode is grounded. R ₁₄ is the seventh resistor, SCR
It is inserted between the gate and cathode of _Q2 . D ₄
is a diode, which is connected in antiparallel to the relay coil Ry. SW ₂ is the relay coil Ry
One end of the switch is grounded and the other end is connected to the power line 4 via the load 7.

Furthermore, the operation of the receiving circuit of the present invention will be explained in detail.

The power supply voltage S ₁ applied to the power line 4 is appropriately divided by the resistors R ₅ and R ₆ of the gate pulse generation circuit 11, and the divided voltage is sent to the inverter via the resistor R ₇ .
Apply to the series circuit of G ₂ and G ₃ . Here, the rectifier circuit 14 rectifies the power supply voltage _S1 and outputs a substantially constant voltage. Therefore, one pole of capacitor C ₄ is connected to said inverter G ₂ via switch SW ₁ .
When connected to the output terminal of the gate pulse generating circuit 11, that is, the capacitor C ₄ and the resistor R ₁₀
A gate pulse _S2 is output to the connection point.

On the other hand, when the control signal S 3 is input from the transmitting circuit 5 to the input end of the coupler 8 via the power line 4, the coupler 8 selectively sends only _{the predetermined control signal S 3 to} the subsequent limit circuit 9. Given. The limit circuit 9 outputs a signal _S4 that corresponds to V/2 with respect to the O level of the control signal _S3 (V is the peak value of the power supply voltage _S1 ).

The signal S ₄ is a reversely connected diode
A signal _S5 whose pulse height is _V1 (V/ _2〓V1 <V) is generated through _D1 , second and first resistors _R4 and _R3 , and is input to one input of the NOR circuit NOR. given at the end. Further, the gate pulse _S2 is applied to the other input terminal of the NOR circuit NOR via a third resistor _R8 . As a result, the signal _S6 is outputted to the output terminal of the NOR circuit NOR.

The transistor during the pulse width t ₁ of the signal S ₆
Q ₁ is made conductive and the second capacitor C ₇ is charged. During the pulse interval _t2 of the signal _S6 , the charge in the second capacitor _C7 is discharged, but a subsequent pulse causes the transistor to be discharged again.
Since Q ₁ is conductive, said second capacitor C ₇
is further charged. By repeating this operation several times, the charging voltage of the second capacitor _C7 exceeds the predetermined voltage _V2 , and the SCR is passed through the sixth resistor _R13 .
Give a control signal to the gate of _Q2 . Therefore SCR Q ₂
conducts and energizes the relay coil Ry of the relay circuit 13. As the relay coil Ry is energized,
Drive switch SW ₂ to operate load 7.

In addition, the movable contact of switch SW ₁ is connected to inverter G ₃ .
, the signal S ₂ will be inverted, and in this case, the signal S ₂ will be at a low level at the beginning of the positive half cycle of the supply voltage S ₁ . Therefore, if the control signal _S3 is given from the transmitting circuit 5 during the period when the signal _S2 is at a low level, the pulse signal _S6 will be obtained at the output of the received signal detection circuit 10, and the relay circuit 13 will operate in the same way as described above. , the power supply to the load 7 is controlled.

Therefore, in the case of having a plurality of receiving circuits, the gate pulse generating circuit 11 generates pulses in different phases, and the transmitting circuit 5 sends out the control signal _S3 at the phase assigned to each receiving circuit. Individual receiver circuits can be selectively controlled. In the example shown in Figure 2, for the receiving circuit where switch SW ₁ is set to the inverter G ₂ side, the phase of the power supply voltage S ₁ is (π, π + θ) (θ is the electrical angle corresponding to the pulse generation period). Control can be performed by whether or not to send the control signal _S3 during the period of
The receiving circuit in which SW ₁ is set on the inverter G ₃ side can be controlled by whether or not to send the control signal S ₃ during the (O, O+θ) phase period of the power supply voltage S ₁ .

As described above, in the receiving circuit of the present invention, one input terminal of the received signal detection circuit is connected to the output terminal of the limit circuit via the series circuit of the first and second resistors and the diode, and The other input end is the third
A fourth NOR circuit connected to the output end of the gate pulse generation circuit through the resistor, and a fourth NOR circuit inserted between the connection point of the first and second resistors and the output end of the rectifier circuit.
and a first capacitor connected in parallel to the fourth low resistor, the relay drive circuit is configured with a collector connected to the output end of the rectifier circuit and a base connected to the received signal detection circuit. a transistor connected to the output terminal of the transistor and whose emitter is grounded via a fifth resistor and a second capacitor;
An anode is connected to the output end of the rectifier circuit via a relay circuit, a gate is connected to a connection point between the fifth resistor and the second capacitor via a sixth resistor, and a cathode is grounded. SCR
and a seventh resistor inserted between the gate and cathode of the SCR, compared to the conventional example shown in FIG. 4, (a) the amplification stage of the received signal detection circuit can be removed one step.

(b) Flip-flops in the relay drive circuit can be removed.

(c) Therefore, miniaturization can be achieved.

(d) At the same time, cost savings can be achieved.

It has the following effects.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the receiving circuit of the present invention, FIG. 3 is an explanatory diagram of the same operation, and FIG. 4 shows a conventional example. 1...Reception circuit, 2...Block filter, 3...
Commercial power supply, 4...Power line, 5...Transmission circuit, 6...Control switch, 7...Load, 8...Coupler, 9...Limit circuit, 10...Received signal detection circuit, 11...Gate pulse generation circuit, 12...Relay drive circuit , 13... Relay circuit, 14... Rectifier circuit, C ₁ to C ₇ ... Capacitor, D ₁ to _{D 4} ... Diode, G ₁ to G ₃ ... Inverter, NOR... NOR circuit, Q ₁ ... Transistor, Q ₂ ...
SCR, R ₁ to R ₁₄ ...resistance, Ry...relay coil,
SW ₁ , SW ₂ ...Switch, TR...Transformer, ZD...Zener diode.

Claims (1)

[Claims] 1 A receiving circuit connected to a power line connected to a commercial power source via a block filter and driven by a control signal transmitted via the power line from a transmitting circuit connected to the power line, the receiving circuit being driven by a control signal transmitted via the power line from a transmitting circuit connected to the power line. a coupler connected to the power line to allow only the control signal to pass; a limit circuit connected to the output end of the coupler to regulate the input control signal to a predetermined amplitude; a gate pulse generation circuit that generates a pulse with a width of 1000 kHz, a received signal detection circuit that is connected to the output terminal of the limit circuit and the output terminal of the gate pulse generating circuit and detects when both signals arrive at the same time, and the received signal a relay drive circuit connected to the output end of the detection circuit, a relay circuit driven by the relay drive circuit, a load operated by the relay circuit, the gate pulse generation circuit connected to the power line, and the received signal. In a receiving circuit comprising a detection circuit, the relay drive circuit, and a rectifier circuit that applies a DC voltage to the relow circuit, the received signal detection circuit has one input terminal connected to a first and second resistor connected in series with a diode. a NOR circuit connected to the output end of the limit circuit through a circuit, and whose other input end is connected to the output end of the gate pulse generation circuit through a third resistor;
a fourth resistor inserted between the connection point of the resistor and the output end of the rectifier circuit, and a first capacitor connected in parallel to the fourth resistor, and the relay drive circuit has a collector is connected to the output end of the rectifier circuit, and the base is connected to the output end of the received signal detection circuit, and the emitter is grounded via a fifth resistor and a second capacitor; It is connected to the output end of the rectifier circuit via the relay circuit, and its gate is connected to the connection point between the fifth resistor and the second capacitor via a sixth resistor, and its cathode is grounded. A receiving circuit comprising an SCR and a seventh resistor inserted between the gate and cathode of the SCR.