JPS6140137B2 - - Google Patents
Info
- Publication number
- JPS6140137B2 JPS6140137B2 JP1847779A JP1847779A JPS6140137B2 JP S6140137 B2 JPS6140137 B2 JP S6140137B2 JP 1847779 A JP1847779 A JP 1847779A JP 1847779 A JP1847779 A JP 1847779A JP S6140137 B2 JPS6140137 B2 JP S6140137B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor substrate
- metal film
- group
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の保護方法、とくに、樹脂
絶縁材料を用いた半導体装置の保護方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for protecting a semiconductor device, and particularly to a method for protecting a semiconductor device using a resin insulating material.
従来の樹脂絶縁材料による半導体集積回路装置
の最も一般的な保護方法及びその問題点を第１図
ａ，ｂにより説明する。 The most common method of protecting a semiconductor integrated circuit device using a conventional resin insulating material and its problems will be explained with reference to FIGS. 1a and 1b.
図において、１はシリコン等の半導体基板を示
し、その表面層には、たとえば、PNPトランジス
タが形成されている。この半導体基板１の表面に
はエミツタ、ベース、コレクタ間の絶縁及び保護
用の二酸化シリコン膜２が形成され、さらに、ベ
ース電極３、エミツタ電極４がアルミニウム蒸着
膜により形成されている。 In the figure, reference numeral 1 indicates a semiconductor substrate made of silicon or the like, and a PNP transistor, for example, is formed on its surface layer. A silicon dioxide film 2 for insulation and protection between the emitter, base, and collector is formed on the surface of the semiconductor substrate 1, and furthermore, a base electrode 3 and an emitter electrode 4 are formed of an aluminum vapor-deposited film.
このプレーナ型トランジスタをパツケージング
する場合、図ｂに示すように、半導体基板１を外
部電極取り出し用リード線８に固定し、エミツタ
電極４に金あるいはアルミニウムのワイヤ５をボ
ンデイングによつて取り付ける。以上のように、
各配線が行なわれた半導体基板１は表面をアンダ
ーコート用樹脂層６により被覆保護した後、機械
的強度を持たせるためと外気からの保護のため
に、リード線８とボンデイングワイヤ５の基板寄
りの部分を基板１と共にモールド樹脂９に埋め込
んでいる。 When packaging this planar transistor, as shown in FIG. b, the semiconductor substrate 1 is fixed to a lead wire 8 for taking out an external electrode, and a gold or aluminum wire 5 is attached to the emitter electrode 4 by bonding. As mentioned above,
After the surface of the semiconductor substrate 1 on which each wiring has been formed is coated and protected with an undercoat resin layer 6, lead wires 8 and bonding wires 5 are placed close to the substrate in order to provide mechanical strength and protect it from the outside air. is embedded in the mold resin 9 together with the substrate 1.
しかし、上述の半導体回路装置が温度変化を受
け、また、高湿な雰囲気に曝された場合、モール
ド樹脂９とリード線８と半導体基板１との熱膨脹
率の差あるいは吸湿による樹脂９の膨潤に起因し
て、モールド樹脂９と半導体基板１との界面に空
隙が生じる。外気に含まれる水分は、この空隙を
通じて侵入し、半導体基板１の表面層にまで達す
る。一般に、シリコーン、二酸化シリコン等の非
金属材料と樹脂との接着性は水の介入により著る
しく低下する欠点がある。したがつて、上記空隙
を通して半導体基板１の表面層にまで達した水
は、半導体基板１及び二酸化シリコン膜２とアン
ダコート用樹脂層６との接着性を劣化させ、ベー
ス電極３にまで達する。この結果、水の介在によ
りベース、コレクタ間の逆耐圧不良が起こり、半
導体回路としての機能を果さなくなる。 However, when the above-described semiconductor circuit device is subjected to temperature changes or exposed to a high humidity atmosphere, the resin 9 may swell due to the difference in coefficient of thermal expansion between the mold resin 9, the lead wire 8, and the semiconductor substrate 1, or due to moisture absorption. As a result, voids are created at the interface between mold resin 9 and semiconductor substrate 1. Moisture contained in the outside air enters through this gap and reaches the surface layer of the semiconductor substrate 1. Generally, there is a drawback that the adhesion between a nonmetallic material such as silicone or silicon dioxide and a resin is significantly reduced by the intervention of water. Therefore, the water that has reached the surface layer of the semiconductor substrate 1 through the above-mentioned void deteriorates the adhesion between the semiconductor substrate 1 and the silicon dioxide film 2 and the undercoat resin layer 6, and reaches the base electrode 3. As a result, a reverse withstand voltage failure occurs between the base and the collector due to the presence of water, and the circuit no longer functions as a semiconductor circuit.
本発明の目的は、上記した従来の半導体装置の
保護方法の欠点をなくし、信頼性の高い半導体装
置を提供しようとするものである。 An object of the present invention is to eliminate the drawbacks of the conventional semiconductor device protection methods described above and provide a highly reliable semiconductor device.
本発明の特徴とするところは、表面部に半導体
素子が形成されている半導体基板上にこの半導体
素子を取り囲むように二酸化シリコン膜等の絶縁
膜を介してAl等からなる金属膜帯を設けると共
に前記半導体素子と金属膜帯を覆うようにフエニ
ルラダーシリコーン樹脂からなるアンダコート用
樹脂層を形成し、前記絶縁膜とアンダコート樹脂
層との界面に水の侵入があつても劣化しない接着
層を形成し、従来技術の欠点をなくそうとするも
のである。本発明はその目的に対して種々の高分
子樹脂について検討し、上記の樹脂が数々の点で
優れたものであることを確認した。 The present invention is characterized by providing a metal film band made of Al or the like through an insulating film such as a silicon dioxide film so as to surround the semiconductor element on a semiconductor substrate having a semiconductor element formed on the surface thereof. An undercoat resin layer made of phenyl ladder silicone resin is formed to cover the semiconductor element and the metal film band, and an adhesive layer that does not deteriorate even if water enters the interface between the insulating film and the undercoat resin layer. The aim is to eliminate the drawbacks of the prior art. The present invention has investigated various polymer resins for the purpose and confirmed that the above resins are excellent in many respects.
以下に本発明の詳細を半導体集積回路を例とし
て第２図を用いて説明する。図ａは平面図、図ｂ
は側断面図である。 The details of the present invention will be explained below with reference to FIG. 2, taking a semiconductor integrated circuit as an example. Figure a is a plan view, figure b
is a side sectional view.
従来と同様に、表面部にベース、エミツタ領域
の形成されている半導体基板１の表面に二酸化シ
リコン膜２を形成した後、、周知の真空蒸着法及
びホトエツチング法により、ベース電極３とエミ
ツタ電極４を形成する際に、同時に、ベース電極
３を取り囲むように金属膜帯７を形成し、さら
に、リードワイヤ５をエミツタ電極４に、リード
ワイヤ（図示されていない）をベース電極３にボ
ンデイングした後、フエニルラダーシリコーン樹
脂からなるアンダコート樹脂層６を形成する。そ
の後、外部電極取り出し用リード線８に半導体基
板１の底面を固定してから、従来と同様にモール
ド樹脂９に埋め込む。 As in the conventional method, after forming a silicon dioxide film 2 on the surface of the semiconductor substrate 1 on which the base and emitter regions are formed, a base electrode 3 and an emitter electrode 4 are formed by well-known vacuum evaporation and photoetching methods. At the same time, a metal film band 7 is formed to surround the base electrode 3, and the lead wire 5 is bonded to the emitter electrode 4, and the lead wire (not shown) is bonded to the base electrode 3. , an undercoat resin layer 6 made of phenyl ladder silicone resin is formed. Thereafter, the bottom surface of the semiconductor substrate 1 is fixed to the lead wire 8 for taking out external electrodes, and then embedded in a mold resin 9 as in the conventional case.
本発明に用いるオルガノ・ラダーシリコーン樹
脂は下記の構造をもつたポリオルガノ・シルセス
キオキサンである。 The organo-ladder silicone resin used in the present invention is a polyorgano-silsesquioxane having the following structure.
ただし、式中、R1、R2、R3、R4はフエニル
基、ハロゲン化フエニル基、ハロゲン化メチルフ
エニル基、メチル、エチル、プロピル、ブチル、
アミル、ヘキシル等のアルキル基であり、R1、
R2、R3、R4は同一基または異なる基であり、ｎ
は正の整数である。具体的には、ポリフエニル・
シルセスキオキサン、ポリフエニル・イソブチル
シルセスキオキサン、ポリ（ｍ−クロロフエニ
ル）シルセスキオキサン、ポリフエニル・アミル
ヘキシルシルセスキオキサン、ポリフエニル・ｍ
−クロロフエニルシルセスキオキサン、ポリメチ
ルシルセスキオキサン等である。 However, in the formula, R 1 , R 2 , R 3 , and R 4 are phenyl group, halogenated phenyl group, halogenated methylphenyl group, methyl, ethyl, propyl, butyl,
It is an alkyl group such as amyl or hexyl, and R 1 ,
R 2 , R 3 and R 4 are the same group or different groups, and n
is a positive integer. Specifically, polyphenyl
Silsesquioxane, polyphenyl isobutylsilsesquioxane, poly(m-chlorophenyl)silsesquioxane, polyphenyl amylhexylsilsesquioxane, polyphenyl m
-chlorophenylsilsesquioxane, polymethylsilsesquioxane, etc.
本発明の効果は、金属膜帯７とアンダコート用
樹脂層６との接着性の水による劣化がないため
に、前述した半導体基板１の表面層にまで浸入し
た水は金属膜帯７とアンダコート用樹脂層６との
接着部で遮断され、この半導体回路内には浸入せ
ず、したがつて、コレクタ、ベース間の逆耐圧不
良が起らないことにある。また、アンダコート用
樹脂層６として、オルガノラダーシリコーン樹脂
を用いているので、アンダコート用樹脂層６の界
面分極等に基因するリーク電流が生ぜず、さら
に、ワイヤ５と電極４との接続が確実である。 The effect of the present invention is that since the adhesive property between the metal film band 7 and the undercoat resin layer 6 is not deteriorated by water, the water that has penetrated into the surface layer of the semiconductor substrate 1 described above will be able to connect the metal film band 7 and the undercoat. It is blocked by the adhesive part with the coating resin layer 6 and does not penetrate into the semiconductor circuit, so that a reverse breakdown voltage failure between the collector and the base does not occur. Furthermore, since organoladder silicone resin is used as the undercoat resin layer 6, leakage current due to interfacial polarization of the undercoat resin layer 6 does not occur, and the connection between the wire 5 and the electrode 4 is prevented. It is certain.
以下、本発明をさらに具体的実施例によつて詳
細に説明する。 Hereinafter, the present invention will be explained in more detail with reference to specific examples.
実施例 １
第２図ａ，ｂに示すように、プレーナ型トラン
ジスタに適用した。半導体基板１上にAlからな
るエミツタ電極４とベース電極３を形成すると
き、同時にベース電極３を取り囲むようにAlか
らなる金属膜帯７を形成する。しかる後、半導体
基板１をリードフレームに固定し、金属線によつ
てエミツタ電極４とベース電極３とをそれぞれ外
部リード線と接続する。その後、フエニルラダー
シリコーン樹脂（実施例ではポリフエニル・シル
セスキオキサンを用いた。）のアニソール溶液を
半導体基板１の表面に塗布し、所定の温度（200
〜300℃）で加熱処理してアンダコート用樹脂層
６を形成し、さらにその外側をモールド樹脂９、
たとえばエポキシ樹脂によつて樹脂封止した。Example 1 As shown in FIGS. 2a and 2b, the present invention was applied to a planar transistor. When forming the emitter electrode 4 and base electrode 3 made of Al on the semiconductor substrate 1, a metal film band 7 made of Al is simultaneously formed so as to surround the base electrode 3. Thereafter, the semiconductor substrate 1 is fixed to a lead frame, and the emitter electrode 4 and the base electrode 3 are respectively connected to external lead wires using metal wires. Thereafter, an anisole solution of phenyl ladder silicone resin (polyphenyl silsesquioxane was used in the example) was applied to the surface of the semiconductor substrate 1, and the temperature was increased to 200°C.
~300℃) to form an undercoat resin layer 6, and the outside thereof is coated with mold resin 9,
For example, it was sealed with epoxy resin.
以上のように、本発明にしたがつて形成したサ
ンプルを通常広く行なわれている加圧浸水試験
（120℃、２気圧の飽和蒸気圧中へ放置）によつ
て、強制劣化試験を行ない、従来品と比較した。 As described above, samples formed according to the present invention were subjected to a forced deterioration test using the commonly widely used pressurized water immersion test (standing in saturated vapor pressure of 2 atm at 120°C), and compared with the product.
その一例として、トランジスタのコレクタとベ
ース間の逆耐圧特性の不良発生情況を調べた結果
を第３図９，１０に示した。図によれば、従来品
は９に示すように高々10時間のテストにしかもた
ないが、本発明を実施したサンプルは１０に示す
ように30時間以上のテストにも十分に耐え、不良
は発生していない。 As an example, FIGS. 9 and 10 show the results of investigating the occurrence of failures in reverse breakdown voltage characteristics between the collector and base of transistors. According to the figure, the conventional product can withstand a test of at most 10 hours as shown in 9, but the sample using the present invention can withstand a test of more than 30 hours as shown in 10, with no defects. I haven't.
さらに、この効果を確かめるために、熱酸化二
酸化シリコン膜表面上に形成したフエニルラダー
シリコーン樹脂膜と、真空蒸着によつて形成した
Al膜表面上に形成したフエニルラダーシリコー
ン樹脂膜を、それぞれ前述した加圧浸水試験にか
けたときの接着強度の変化を調べた結果、熱酸化
シリコン膜表面に形成したフエニルラダーシリコ
ーン樹脂は約１時間の放置でほとんど接着強度が
なくなるのに対して、Al膜表面上に形成してフ
エニルラダーシリコーン樹脂の接着性は10時間後
も全く低下しない。 Furthermore, in order to confirm this effect, we used a phenyl ladder silicone resin film formed on the surface of a thermally oxidized silicon dioxide film and a phenyl ladder silicone resin film formed on the surface of a thermally oxidized silicon dioxide film.
As a result of examining the change in adhesive strength when phenyl ladder silicone resin films formed on the surface of an Al film were subjected to the above-mentioned pressure water immersion test, it was found that the phenyl ladder silicone resin films formed on the surface of a thermally oxidized silicon film were approximately In contrast, the adhesive strength of the phenyl ladder silicone resin formed on the surface of the Al film does not deteriorate at all even after 10 hours, whereas the adhesive strength is almost lost after one hour of standing.
これらの事実から、本発明によつて、トランジ
スタの耐湿性が従来と比べて著るしく改善される
ことがわかる。 From these facts, it can be seen that the present invention significantly improves the moisture resistance of the transistor compared to the conventional one.
実施例 ２
実施例１では、本発明を単体トランジスタに適
用した場合について説明したが、本実施例では、
半導体集積回路に適用した場合について述べる。
この場合、半導体基板の中央部には半導体素子が
形成され、その周囲にボンデイングパツドが設け
られている。このボンデイングパツドの外側に、
幅30μｍ、厚さ１μｍのAlからなる金属膜帯を
形成した。半導体基板をパツケージに固定し、ボ
ンデイングパツドと外部接続端子とを金属線で接
続したのち、フエニルラダーシリコーン樹脂で半
導体基板表面を被覆した。Example 2 In Example 1, the case where the present invention was applied to a single transistor was explained, but in this example,
A case where the present invention is applied to a semiconductor integrated circuit will be described.
In this case, a semiconductor element is formed in the center of the semiconductor substrate, and bonding pads are provided around the semiconductor element. On the outside of this bonding pad,
A metal film band made of Al having a width of 30 μm and a thickness of 1 μm was formed. After fixing the semiconductor substrate to a package and connecting the bonding pads and external connection terminals with metal wires, the surface of the semiconductor substrate was coated with phenyl ladder silicone resin.
実施例１と同様に加圧浸水試験を行なつた結
果、不良の発生はほとんどなく、単体トランジス
タの場合と同様な効果が得られた。 A pressurized water immersion test was conducted in the same manner as in Example 1, and as a result, there were almost no defects, and the same effects as in the case of a single transistor were obtained.
実施例１、２で得られた本発明による効果は、
金属膜帯として、Alを用いた場合であるが、そ
のほかに、Cr、Mo、Ni、Cu、Feなどについて
も同様な効果が得られる。 The effects of the present invention obtained in Examples 1 and 2 are as follows:
Although Al is used as the metal film band, similar effects can be obtained with other materials such as Cr, Mo, Ni, Cu, and Fe.
以上説明したところから明らかなように、本発
明によればすぐれた耐湿性、したがつて高信頼性
の半導体装置を得ることができる。 As is clear from the above description, according to the present invention, a semiconductor device with excellent moisture resistance and therefore high reliability can be obtained.
第１図ａ，ｂはそれぞれ従来の半導体トランジ
スタの平面図および断面図、第２図ａ，ｂはそれ
ぞれ本発明を適用した場合の半導体トランジスタ
の平面図および断面図、第３図は耐湿試験におけ
る本発明による半導体トランジスタと従来の半導
体トランジスタのコレクタ、ベース間の逆耐圧特
性不良の発生率を示すグラフである。
図において、１：半導体基板、２：二酸化シリ
コン膜、３：ベース電極、４：エミツタ電極、
５：ボンデイングワイヤ、６：アンダコート用樹
脂層、７：金属膜帯、８：外部電極取り出し用リ
ード線、９：モールド樹脂。
Figures 1a and b are a plan view and a cross-sectional view of a conventional semiconductor transistor, respectively. Figures 2a and b are a plan view and a cross-sectional view of a semiconductor transistor to which the present invention is applied, and Figure 3 is a diagram of a moisture resistance test. 2 is a graph showing the incidence of reverse breakdown voltage characteristic defects between the collector and base of a semiconductor transistor according to the present invention and a conventional semiconductor transistor. In the figure, 1: semiconductor substrate, 2: silicon dioxide film, 3: base electrode, 4: emitter electrode,
5: bonding wire, 6: resin layer for undercoat, 7: metal film band, 8: lead wire for taking out external electrode, 9: mold resin.
Claims (1)
導体表面上に絶縁膜を介して上記半導体素子を取
り囲むように設けられた金属膜帯と、上記半導体
素子を覆い、かつ上記金属膜帯上に延伸している
下記の構造をもつたポリオルガノ・シルセスキオ
キサン樹脂層とを具備したことを特徴とする半導
体装置。 ただし、式中、R1、R2、R3、R4はフエニル
基、ハロゲン化フエニル基、ハロゲン化メチルフ
エニル基、メチル、エチル、プロピル、ブチル、
アミル、ヘキシル基等のアルキル基であり、
R1、R2、R3、R4は同一基または異なる基であ
り、ｎは正の整数である。[Scope of Claims] 1 A semiconductor element formed on a semiconductor substrate, a metal film band provided on the surface of the semiconductor so as to surround the semiconductor element via an insulating film, and a metal film band covering the semiconductor element and 1. A semiconductor device comprising a polyorgano-silsesquioxane resin layer having the following structure extending on a metal film band. However, in the formula, R 1 , R 2 , R 3 , and R 4 are phenyl group, halogenated phenyl group, halogenated methylphenyl group, methyl, ethyl, propyl, butyl,
It is an alkyl group such as amyl or hexyl group,
R 1 , R 2 , R 3 and R 4 are the same group or different groups, and n is a positive integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1847779A JPS55111148A (en) | 1979-02-21 | 1979-02-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1847779A JPS55111148A (en) | 1979-02-21 | 1979-02-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55111148A JPS55111148A (en) | 1980-08-27 |
| JPS6140137B2 true JPS6140137B2 (en) | 1986-09-08 |
Family
ID=11972714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1847779A Granted JPS55111148A (en) | 1979-02-21 | 1979-02-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55111148A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2613128B2 (en) * | 1990-10-01 | 1997-05-21 | 三菱電機株式会社 | Semiconductor device |
| US6143855A (en) * | 1997-04-21 | 2000-11-07 | Alliedsignal Inc. | Organohydridosiloxane resins with high organic content |
| US6218497B1 (en) | 1997-04-21 | 2001-04-17 | Alliedsignal Inc. | Organohydridosiloxane resins with low organic content |
| US6177199B1 (en) | 1999-01-07 | 2001-01-23 | Alliedsignal Inc. | Dielectric films from organohydridosiloxane resins with low organic content |
| US6218020B1 (en) | 1999-01-07 | 2001-04-17 | Alliedsignal Inc. | Dielectric films from organohydridosiloxane resins with high organic content |
| WO2015088932A1 (en) | 2013-12-09 | 2015-06-18 | 3M Innovative Properties Company | Curable silsesquioxane polymers, compositions, articles, and methods |
| US10370564B2 (en) | 2014-06-20 | 2019-08-06 | 3M Innovative Properties Company | Adhesive compositions comprising a silsesquioxane polymer crosslinker, articles and methods |
| CN106661228A (en) | 2014-06-20 | 2017-05-10 | 3M创新有限公司 | Curable polymers comprising silsesquioxane polymer core and silsesquioxane polymer outer layer and methods |
| US10392538B2 (en) | 2014-06-20 | 2019-08-27 | 3M Innovative Properties Company | Adhesive compositions comprising a silsesquioxane polymer crosslinker, articles and methods |
| JP2017528577A (en) | 2014-09-22 | 2017-09-28 | スリーエム イノベイティブ プロパティズ カンパニー | Curable polymer containing silsesquioxane polymer core, silsesquioxane polymer outer layer, and reactive groups |
| US9957416B2 (en) | 2014-09-22 | 2018-05-01 | 3M Innovative Properties Company | Curable end-capped silsesquioxane polymer comprising reactive groups |
-
1979
- 1979-02-21 JP JP1847779A patent/JPS55111148A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55111148A (en) | 1980-08-27 |
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