JPH0680695B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0680695B2 JPH0680695B2 JP62167264A JP16726487A JPH0680695B2 JP H0680695 B2 JPH0680695 B2 JP H0680695B2 JP 62167264 A JP62167264 A JP 62167264A JP 16726487 A JP16726487 A JP 16726487A JP H0680695 B2 JPH0680695 B2 JP H0680695B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- protective film
- bonding pad
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に外部との電気的接続を
行う金属電極（ボンディングパッド電極）の耐腐蝕性に
優れた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device excellent in corrosion resistance of a metal electrode (bonding pad electrode) for electrically connecting to the outside.
半導体装置の表面から水分や不純物イオンが内部に拡散
すると，当該装置の電気特性が劣化したり電極，配線が
腐食するなど信頼性が劣化する。このため，水分や不純
物イオンなどの拡散を防止するために，従来は装置の表
面にSiN膜，SiO2膜，あるいはPSG膜などの絶縁膜を設け
ていた。外部との電気的接続は、半導体基板に設けられ
たボンディングパッド部の電極表面上の絶縁膜を除去し
た上で当該電極に金属ワイヤを接続することにより行わ
れていた。When moisture or impurity ions diffuse from the surface of the semiconductor device to the inside, the electrical characteristics of the device are deteriorated and the reliability of the device is deteriorated such as corrosion of electrodes and wiring. Therefore, in order to prevent the diffusion of moisture and impurity ions, conventionally, an insulating film such as a SiN film, a SiO 2 film, or a PSG film was provided on the surface of the device. The electrical connection to the outside has been performed by removing the insulating film on the electrode surface of the bonding pad portion provided on the semiconductor substrate and then connecting a metal wire to the electrode.
第４図は従来の半導体装置を示す断面図である。半導体
素子が形成され，その裏面がリードフレーム108に固定
された半導体基板101の表面には金属電極102が設けら
れ、この金属電極102及び半導体基板の101の表面を覆っ
て保護膜106が設けられている。この金属電極102上に設
けられた保護膜106の所定の部分が除去されボンディン
グパッド部分103が形成されている。このボンディング
パッド部分103において金属電極102は金属ワイヤー104
の一端とワイヤーボンディング部105を介して接続され
ている。この金属ワイヤー102の他端はワイヤーボンデ
ィング部105を介してリードフレーム電極端子109と接続
されている。FIG. 4 is a sectional view showing a conventional semiconductor device. A semiconductor element is formed, and a metal electrode 102 is provided on the surface of a semiconductor substrate 101 whose back surface is fixed to a lead frame 108, and a protective film 106 is provided to cover the metal electrode 102 and the surface of the semiconductor substrate 101. ing. A predetermined portion of the protective film 106 provided on the metal electrode 102 is removed to form a bonding pad portion 103. In this bonding pad portion 103, the metal electrode 102 is connected to the metal wire 104.
Is connected to one end of the wire via a wire bonding portion 105. The other end of the metal wire 102 is connected to the lead frame electrode terminal 109 via the wire bonding portion 105.
半導体基板101に金属ワイヤを接続する手順は以下の通
りである。保護膜106が部分的に除去され、ボンディン
グパッド部103が形成された半導体基板101が、リードフ
レーム108上に固着され、周知の技術を用いて金属ワイ
ヤ104の一端がボンディングパッド部の金属電極102に接
続され、他端がリードフレームの電極端子に接続され
る。しかる後に当該半導体基板101,金属ワイヤ104,リー
ドフレーム108,リードフレーム電極端子109の一部が樹
脂でおおわれ封止される。The procedure for connecting the metal wire to the semiconductor substrate 101 is as follows. The protective film 106 is partially removed, and the semiconductor substrate 101 on which the bonding pad portion 103 is formed is fixed onto the lead frame 108, and one end of the metal wire 104 is a metal electrode 102 of the bonding pad portion using a known technique. , And the other end is connected to the electrode terminal of the lead frame. Then, the semiconductor substrate 101, the metal wire 104, the lead frame 108, and a part of the lead frame electrode terminal 109 are covered with resin and sealed.
上述した従来の半導体装置は、ボンディングパッド電極
が露出した状態で金属ワイヤが接続され、しかる後に樹
脂封止される。従って、ボンディングパッド部の金属電
極の表面は部分的に何らの保護膜も設けられないまま樹
脂にさらされる。従って，水分および不純物の侵蝕を直
接的に受けるため、当該ボンディングパッド電極の腐食
が容易に起き半導体装置の配線が切断され不良を発生し
易いという欠点がある。In the conventional semiconductor device described above, the metal wire is connected with the bonding pad electrode exposed, and then the resin is sealed. Therefore, the surface of the metal electrode of the bonding pad portion is partially exposed to the resin without any protective film. Accordingly, since the bonding pad electrode is directly corroded by moisture and impurities, the bonding pad electrode is easily corroded, and the wiring of the semiconductor device is cut off, which easily causes a defect.
本発明の半導体装置は半導体基板に設けられ外部と電気
的に接続される金属電極と、この金属電極に接続される
金属ワイヤと、この金属電極と金属ワイヤとの接続部分
を覆う保護膜とを有している。A semiconductor device of the present invention includes a metal electrode provided on a semiconductor substrate and electrically connected to the outside, a metal wire connected to the metal electrode, and a protective film covering a connecting portion between the metal electrode and the metal wire. Have
また，本発明の半導体装置は，外部との電気的接続を行
うためのボンディングパッド電極部を除く半導体装置表
面全体を覆う第１の保護膜と，ボンディングパッド電極
部に金属ワイヤが接続された後にボンディングパッド電
極表面、金属ワイヤ表面を含む半導体装置表面全体を覆
う第２の保護膜とが設けられる。Further, in the semiconductor device of the present invention, after the first protective film covering the entire surface of the semiconductor device except the bonding pad electrode portion for electrically connecting to the outside and the metal wire is connected to the bonding pad electrode portion. A second protective film is provided to cover the entire surface of the semiconductor device including the surface of the bonding pad electrode and the surface of the metal wire.
さらに，封止用樹脂材とリードフレームとの密着性を高
めるために、この半導体基板を固定するリード・フレー
ムの表面（表面・裏面）にも第２の保護膜を形成するも
のである。Further, in order to improve the adhesion between the sealing resin material and the lead frame, a second protective film is formed on the front surface (front surface / back surface) of the lead frame fixing this semiconductor substrate.
次に本発明について図面を参照して説明する。第１図は
本発明の第１の実施例を説明する半導体装置の概略断面
図である。図に於て第４図と同記号は同一機能を有する
物質を示す。106は半導体装置101表面に設けられた第１
の保護膜,107は第２の保護膜である。通常、金属電極10
2およびボンディングパッド部103はアルミニウムを用
い、金属ワイヤ104は金又はアルミニウムを用いる。第
１の保護膜106としてはCVD法で形成されたPSG膜（膜厚
0.8μｍ程度）、あるいはプラズマCVD法で形成されたSi
N膜（膜厚0.4μｍ程度）を用いる。これらの膜は各々単
独に用いても両者を２層に設けても選択は自由である。
第１の保護膜106の一部が除去されボンディングパッド
部103が設けられた後に半導体装置101がリードフレーム
108上に固着され、しかる後に金属ワイヤ104がボンディ
ングパッド部に接続される。次に、当該金属ワイヤ104
が接続半導体装置101の表面に第２の保護膜105が形成さ
れる。当該第２の保護膜は極力低温で形成される必要が
あり、このため、第２の保護膜としては300nm以下の波
長のし紫外光を照射しつつ膜堆積を行う光CVD法によっ
て,220〜280℃の温度下で形成可能な絶縁膜を用いた。
上記第２の保護膜に用いる絶縁膜としては，SiO2膜、Si
N膜,SiON膜，Al2O3膜（酸化アルミニウム膜）の中のい
ずれかの膜が使用できる。かかる第２の保護膜が形成さ
れた後に樹脂封止が行われる。ここで、SiO2膜の厚みは
50〜500nmとし、SiN膜の厚みは100〜400nmとし、SiON膜
の厚みは50〜500nmとする。Next, the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view of a semiconductor device for explaining a first embodiment of the present invention. In the figure, the same symbols as in FIG. 4 indicate substances having the same function. Reference numeral 106 denotes a first device provided on the surface of the semiconductor device 101.
The protective film 107 is a second protective film. Usually a metal electrode 10
2 and the bonding pad portion 103 are made of aluminum, and the metal wire 104 is made of gold or aluminum. As the first protective film 106, a PSG film (film thickness formed by the CVD method
0.8 μm) or Si formed by plasma CVD method
An N film (film thickness of about 0.4 μm) is used. These films may be used alone or may be provided in two layers, and the selection is free.
After the part of the first protective film 106 is removed and the bonding pad portion 103 is provided, the semiconductor device 101 is connected to the lead frame.
It is fixed on 108, and then the metal wire 104 is connected to the bonding pad portion. Next, the metal wire 104
A second protective film 105 is formed on the surface of the connection semiconductor device 101. The second protective film needs to be formed at a temperature as low as possible. Therefore, as the second protective film, a film thickness of 220 to 220 is obtained by the photo-CVD method in which film deposition is performed while irradiating ultraviolet light having a wavelength of 300 nm or less. An insulating film that can be formed at a temperature of 280 ° C. was used.
As the insulating film used for the second protective film, SiO 2 film, Si
Any of N film, SiON film, and Al 2 O 3 film (aluminum oxide film) can be used. Resin sealing is performed after the second protective film is formed. Here, the thickness of the SiO 2 film is
The thickness of the SiN film is 50 to 500 nm, the thickness of the SiN film is 100 to 400 nm, and the thickness of the SiON film is 50 to 500 nm.
次に樹脂防止を行った本半導体装置の耐湿性を評価し
た。耐湿性試験は,150℃２気圧の水蒸気釜に試料を入れ
るPCT（プレッシャー・クッカー・テスト）を行い，試
料の不良発生率を調べた。第２図に耐湿性試験の結果を
示す。試料としては，第２の保護膜のない従来の半導体
装置，第２の保護膜として上述した光CVDで形成したSiO
2膜,SiN膜,SiON膜，Al2O3膜それぞれを0.2μｍとした本
発明の半導体装置の５水準，各水準50個を調べた。第２
の保護膜のない従来の半導体装置に比べ，本発明の半導
体装置は耐湿性において各段に優れていることが示され
る。Next, the moisture resistance of this semiconductor device subjected to resin prevention was evaluated. In the moisture resistance test, PCT (pressure cooker test) was conducted by putting the sample in a steam pot at 150 ° C and 2 atm to examine the defect occurrence rate of the sample. Figure 2 shows the results of the humidity resistance test. As a sample, a conventional semiconductor device without a second protective film, SiO formed by the above-mentioned optical CVD as a second protective film
Five levels of the semiconductor device of the present invention in which each of the two films, the SiN film, the SiON film and the Al 2 O 3 film was 0.2 μm, and 50 levels were examined. Second
It is shown that the semiconductor device of the present invention is far superior in moisture resistance to the conventional semiconductor device having no protective film.
第３図は本発明の第２の実施例の概略断面図である。図
に於て、第１図，第３図と同記号は同一機能を有する物
質を示す。201は第２の保護膜,202は封止材であるエポ
キシ樹脂,203はプラスチックパッケージである。FIG. 3 is a schematic sectional view of the second embodiment of the present invention. In the figure, the same symbols as in FIGS. 1 and 3 indicate substances having the same function. 201 is a second protective film, 202 is an epoxy resin as a sealing material, and 203 is a plastic package.
第２の保護膜201は半導体基板101表面に形成されると同
時にリードフレーム108の表裏の一部にも形成され
る、。第２の保護膜である金属酸化膜，シリコン酸化
膜，窒化膜はエポキシ樹脂との密着性がよい。本発明で
は半導体基板をこの表面および露出したリードフレーム
の表裏面に設けられた第２の保護膜である金属酸化膜あ
るいはシリコン酸化膜，あるいは窒化膜を介して，エポ
キシ樹脂と密着させることができる。従って、熱衝撃に
対し強く、エポキシ樹脂とリードフレームとの間に生ず
るクラックが極めて発生しにくい。一方第１の実施例で
説明した半導体装置ではリードフレーム裏面に第２の保
護膜が設けられていないためリードフレーム裏面におけ
るエポキシ樹脂との密着性が悪い。従って熱衝撃により
エポキシ樹脂に生ずるクラックが多く耐湿性は悪い。こ
れに対して本実施例ではリードフレームの表裏面に保護
膜を設けているからエポキシ樹脂との密着性にすぐれて
いる。このため熱衝撃等によりクラックが発生しにく
い。The second protective film 201 is formed on the surface of the semiconductor substrate 101 and, at the same time, formed on a part of the front and back surfaces of the lead frame 108. The metal oxide film, the silicon oxide film, and the nitride film, which are the second protective film, have good adhesion to the epoxy resin. In the present invention, the semiconductor substrate can be adhered to the epoxy resin through the metal oxide film, the silicon oxide film, or the nitride film which is the second protective film provided on the front surface and the exposed front and back surfaces of the lead frame. . Therefore, it is resistant to thermal shock, and cracks that occur between the epoxy resin and the lead frame are extremely unlikely to occur. On the other hand, in the semiconductor device described in the first embodiment, since the second protective film is not provided on the back surface of the lead frame, the adhesion to the epoxy resin on the back surface of the lead frame is poor. Therefore, the epoxy resin has many cracks caused by thermal shock, and the moisture resistance is poor. On the other hand, in this embodiment, since the protective films are provided on the front and back surfaces of the lead frame, the adhesion with the epoxy resin is excellent. Therefore, cracks are less likely to occur due to thermal shock or the like.
前述したPCT法による不良品発生時間を調べると，第１
の実施例１で説明した半導体装置では50時間前後で不良
品が出始めるが，第２の実施例の半導体装置では400時
間でも不良品の発生がなく，優れた耐湿性を示す。これ
は，エポキシ樹脂に生ずるクラックが少ないことと金属
電極上のワイヤ・ボンディング部が保護膜で覆われてい
るため腐食しにくいことによる。When the defective product generation time by the PCT method described above is examined,
In the semiconductor device described in the first embodiment, defective products begin to appear after about 50 hours, but in the semiconductor device of the second embodiment, no defective products occur even after 400 hours, and excellent moisture resistance is exhibited. This is because the epoxy resin has few cracks and the wire bonding part on the metal electrode is covered with the protective film, so that corrosion is unlikely to occur.
以上説明したように本発明は，ボンディングパッド部の
金属電極に金属線を接続した後に半導体基板の表面を保
護膜で覆うことにより，半導体装置の耐湿性を飛躍的に
向上することができる。As described above, according to the present invention, the moisture resistance of the semiconductor device can be dramatically improved by connecting the metal wire to the metal electrode of the bonding pad portion and then covering the surface of the semiconductor substrate with the protective film.
【図面の簡単な説明】 第１図は本発明の第１の実施例の半導体装置の断面図，
第２図は本発明の第１の実施例の半導体装置の効果を示
す耐湿性試験の結果を示す図，第３図は本発明の第２の
実施例の半導体装置の断面図，第４図は従来の半導体装
置の断面図である。 101…半導体素子の形成された半導体装置， 102…金属電極,103…ボンディングパッド部,104…金属
ワイヤ,105…ワイヤ・ボンディング部,106…第１の保護
膜,107…第２の保護膜,108…リード・フレーム,201…第
２の保護膜,202…封止材（エポキシ樹脂）,203…プラス
チックパッケージBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention,
FIG. 2 is a diagram showing the result of a moisture resistance test showing the effect of the semiconductor device of the first embodiment of the present invention, FIG. 3 is a sectional view of the semiconductor device of the second embodiment of the present invention, and FIG. FIG. 6 is a sectional view of a conventional semiconductor device. 101 ... Semiconductor device with semiconductor element formed, 102 ... Metal electrode, 103 ... Bonding pad portion, 104 ... Metal wire, 105 ... Wire bonding portion, 106 ... First protective film, 107 ... Second protective film, 108 ... Lead frame, 201 ... Second protective film, 202 ... Encapsulating material (epoxy resin), 203 ... Plastic package
Claims (1)
される金属電極と、前記金属電極に接続される金属ワイ
ヤと、前記金属電極と前記金属ワイヤとの接続部分を覆
う保護膜とを有する半導体装置において、前記保護膜
が、光化学気相成長法により形成されたSiON膜であっ
て、その膜厚が50〜500nmであることを特徴とする半導
体装置。1. A metal electrode provided on a semiconductor substrate and electrically connected to the outside, a metal wire connected to the metal electrode, and a protective film covering a connecting portion between the metal electrode and the metal wire. The semiconductor device according to the above, wherein the protective film is a SiON film formed by a photochemical vapor deposition method and has a film thickness of 50 to 500 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62167264A JPH0680695B2 (en) | 1987-07-03 | 1987-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62167264A JPH0680695B2 (en) | 1987-07-03 | 1987-07-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6411337A JPS6411337A (en) | 1989-01-13 |
| JPH0680695B2 true JPH0680695B2 (en) | 1994-10-12 |
Family
ID=15846511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62167264A Expired - Lifetime JPH0680695B2 (en) | 1987-07-03 | 1987-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680695B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5121187A (en) * | 1988-10-17 | 1992-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Electric device having a leadframe covered with an antioxidation film |
| JP2653511B2 (en) * | 1989-03-30 | 1997-09-17 | 株式会社東芝 | Semiconductor device cleaning method and cleaning apparatus |
| JPH0396633A (en) * | 1989-09-07 | 1991-04-22 | Nissan Motor Co Ltd | Cylinder number control device for 2 stroke engine |
| JPH03132048A (en) * | 1989-10-18 | 1991-06-05 | Matsushita Electron Corp | Semiconductor device |
| US5695569A (en) * | 1991-02-28 | 1997-12-09 | Texas Instruments Incorporated | Removal of metal contamination |
| US5718763A (en) * | 1994-04-04 | 1998-02-17 | Tokyo Electron Limited | Resist processing apparatus for a rectangular substrate |
| JP4506478B2 (en) * | 2005-01-18 | 2010-07-21 | 株式会社デンソー | Pressure sensor |
| JP6579653B2 (en) * | 2015-06-24 | 2019-09-25 | ローム株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5852331B2 (en) * | 1976-01-30 | 1983-11-22 | 株式会社日立製作所 | Semiconductor device and its manufacturing method |
| JPS53103375A (en) * | 1977-02-22 | 1978-09-08 | Toshiba Corp | Semiconductor device |
| JPS56162844A (en) * | 1980-05-19 | 1981-12-15 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS5889930U (en) * | 1981-12-12 | 1983-06-17 | 日本電気ホームエレクトロニクス株式会社 | semiconductor equipment |
| JPS6085548A (en) * | 1983-10-17 | 1985-05-15 | Nec Corp | Integrated circuit device |
-
1987
- 1987-07-03 JP JP62167264A patent/JPH0680695B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6411337A (en) | 1989-01-13 |
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