JPS6140952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention records a group of closely spaced entities around successive stations and calculates the time of each entity at each station to generate "Timingsplit" information. This invention relates to a high-resolution timekeeping and recording device for recording. The device is preferably used on a racetrack, such as on a race track where horses pass through the Farron bars and their times are recorded substantially instantaneously at each Farron bar.

It is well known to have individual competitive animals, such as horses, carry individual transmitters that communicate with separate detectors. For example, conventionally buried loops are
It was installed on the truck. These buried loops sense the passage of a transmitter mounted on a competitive object, such as a horse, over these loops. An identification circuit senses the passage of each competitor at each station. U.S. Patent No. 5, issued March 5, 1974, entitled “Race Call System.”
Please refer to No. 3795907. Traditionally, such timing counters were not concerned with discrete times at the stations passed. They were simply about the order of passage or calls. For fast passing racehorses, such an indicator displayed the order of those horses' passing.

Facilities were provided to display the spatial separation between these passing animals. For example, referring to the above-mentioned US Pat. No. 3,795,907, one timing counter was approximately equal to the average speed of a race horse. By counting the intervals between successive recordings, an approximation to the passing spatial intervals between racehorses is interpolated.

Knowing the exact times of each competitor at separate stations along a path such as a race course can be very useful information. This information is referred to as a "timepiece." For example, timepiece information is extremely useful to the person in charge of handicaping horse racing. In horse racing handicap, it is necessary to accurately know the changing speed of the animals in order to handicap them so that the races come to a close as a group. Knowing that some animals have slow starts and fast finishes while others have fast starts and slow finishes is essential for competitive handicaps.

Additionally, this same information is useful to horse owners, trainers, and jockeys alike. Best results are obtained if the animal can be run over a known portion of the race course to take advantage of the animal's unique speed variations on the race course. It is very useful to record timed details that form this essential time information.

US Patent No. 23, 1976
No. 3,946,312 discloses an apparatus and method for such timekeeping. In this device, the antenna loop was placed at predetermined locations around the race track. A plurality of entities or competitors pass successively over the loop, preferably attached to the Farron rod, and simultaneously carry transmitters arranged to transmit low radio frequencies at separate frequencies for each competitor. When, a separate fragment time occurred. In this related patent, a single timer is serially connected to a series of counters. The exposed latch device stops this counter in sequence. One counter stops for each station passed. The fragment time thus generated appears in each counter.

A device is disclosed for displaying the elapsed time for each of a plurality of entities, such as a horse race, from a starting point to a series of spaced apart stations, such as a farlong bar, along a path of travel, such as a race track. . Preferably each of the entities includes a radio frequency transmitter carried by each entity, such as a transmitter worn on the horse's forehead. Each transmitter is
It emits a radio frequency signal that is isolated to that entity. A radio frequency receiving means, such as a loop embedded in the truck, is located at each of the stations and receives the signals from each transmitter on each entity as it passes within the reception area of each station. Receive intervals. The receiving means is in communication with detector means, which is adapted to identify and detect each isolated radio frequency and to block the remaining isolated radio frequencies. The detector means are
Generates an output signal that has two functions. 1st
At this point, a marking signal is generated to identify the entity passing through the station. Second,
A clocked timing counter has the instantaneous count recorded with a latch. The activation circuit connects the marking information to the freeze clock count and sequentially transfers the marking information to the random access memory. The final product of the apparatus and method of the present invention is that each entity has its identity and time of passage recorded at each station as it progresses around the travel path. Conventional information recall and printout techniques provide an apparatus for obtaining timing strips for competitions such as horse races.

It is an object of the present invention to load into random access memory the marked times of each entity passing through each station of a given path, such as a race horse passing through farlong bars along a track. be. According to this aspect of the invention, the main clock sends its output to a group of serially connected time 10
Send to advance counter. These counters connected in parallel to appropriate storage latches can freeze their counts into signals at the storage latches.
Separate signals from each separate entity are generated as each entity passes the recording station. These generated signals provide labeled identification and simultaneously cause parallel connected latches to record and store time information. This recorded and stored time information is then read by the control central processing unit, which further transfers the recorded time information to a random access memory. Random access memory sequentially records this indicator and time information for subsequent retrieval.

The advantage of this disclosed device is that it
Data is generated. Moreover, this device is not loaded with timing information other than true external events. Placing false information on this device is virtually excluded.

Another advantage of the invention is that it does not require serially connected counts of multiple groups, each group representing one competitor. Rather, only a single counter is needed that is randomly read at discrete microsecond intervals.

Another advantage of the invention is that a timing strip is generated for each competitor. In the case of horse racing on race tracks, it is possible to determine fractional times with greater accuracy than visual timing. At the current speeds and densities of horse racing, valuable timekeeping information can be obtained with the disclosed device and not with human timers spaced along many points along the race track.

Another advantage of the invention is that the final result of the apparatus is conveniently loaded into random access memory. This random access memory is programmatically read to release this information in any number of desired formats. For example, random
The access memory releases, for each horse only, that horse's times of passing successive stations spaced along the track. As another example of a random access memory read, the memory can determine the order or calls of multiple horses as they pass, as well as the discrete times of those horses' passes at any station. Therefore, improved handy cap attachment is possible. Horse owners, trainers, and jockeys can routinely learn and use their animals' unique racing patterns to their advantage.

Another advantage of the present invention is that it exposes a preferred format for loading race information into random access memory. In accordance with this aspect of the invention, a continuously running series time decimal counter is connected in parallel with each storage latch. Each of these latches is further connected to a marking circuit. The random access memory is loaded with accurate timing information by means of sequentially transferring from each storage latch through the marking circuit to the random access memory up to the closest desired timing interval. For example, 1/5 second is generally used in race and track timing, but
This device can operate in 1/100 seconds.

Another object of the invention is that the device is capable of receiving and comparing time and list data regarding each entity. For example, in the case of horse racing, horse owner, trainer, jockey, and other information may be conveniently listed and retrieved. The results can be teletyped from the device using a conventional teletype output that provides a complete progression of one race.

The transmitter mounted on the competitor surrounds a card 18 on which a battery 19 and appropriate electrical elements are mounted in connection with a printed spiral loop 22 which provides the inductance and radiating elements for the transmitter. The card 18 is mounted in a pouch 23 on the forehead 25 between the eyes of a competitor, such as a horse 28. The outside of the bag is numbered, such as 1, 2, 3, etc., which is a specific identification number for a particular horse or other competitor. Bag 23 thus provides not only a holding bag for sending card 18 but also visual competitor identification. The electrical circuit elements 21 shown in FIGS. 6 and 7 include a 1 KHz free-running multivibrator 31 that activates an electrical switch or gate 32 to provide a square wave output to a high frequency oscillator 35. In the oscillator 35, an LC circuit 38 is coupled within the oscillator circuit. The multivibrator 31 includes a set of transistors 40,
It is of conventional design coupled with a suitable resistor 41 and capacitor 42 chosen to make the multivibrator free-running at 1 KHz or other preselected frequency within the audible range. The output from multivibrator 31 turns off the oscillator and changes the frequency rate of switch 32 (1KHz).
is applied to the base of transistor 45 of switch 32 to provide a square wave output through diode 46 and capacitor 47 to the base of transistor 49 of high frequency oscillator 35 to turn it off.

This oscillator is connected to the inductance of the loop 22 and the capacitor 5 forming a tank circuit for the oscillator.
It is specified to oscillate at a frequency determined by 1. The aforementioned loop 22 is printed on the card 18 and has a predetermined inductance and shape that is ideally constant for all cards, so that in practice the frequency-determining control element is the capacitor 51. . Thus the card for each competitor has a selected value for capacitor 51, so that
The frequency output of the high frequency oscillator 35 has a separate and different frequency for each card to identify each competitor by frequency. It can be seen that the output from the transmitter on card 18 is indicative of a particular competitor.

This system is suitable for low RF frequency ranges, i.e. approx.
With the spacing between transmitter frequencies being 10KHz
Although a range of 350 KHz or less has been found to be most satisfactory, spacings narrower or wider than 10 KHz can also be used within the structure of the present invention. For example, it has been found that good discrimination and differentiation between competitors can be obtained with a spacing or separation of 5KHz. loop 54
constitute a cable having an outer shield connected at one end to the inner conductor, and at the other end the outer shield with its inner conductor connected to a switch 59 for connecting the inner conductor to a common coaxial wiring. Grounded.

This loop system acts as a closed loop untuned transformer exhibiting a 90° phase relationship between the voltage and current induced in the system as they pass over the loop. Switch 59 is a relay activated by appropriate switching (not shown) and then switches 54A, 54B, 5 of FIG.
Selected ones of the antenna loops, designated 4C, 54D, and the following, are included in or excluded from the activation circuit.

Since the coaxial loop is provided underground just below the surface 68 of the race track, it is completely hidden from and does not interfere with the racing competitors. Also, while it is within the practical scope of the device to have a loop above or around the sensing station, there are clear aesthetic and practical advantages to having it underground.

The loop should traverse the entire width of the useful portion of the track. The outlet length 69 and return portion 70 are conveniently spaced approximately one step apart. As mentioned above, the transmitter card 18 is attached to the competitor's forehead 25. In this position, the radiation surface of the coil 22 is
It is arranged to be oriented at the most appropriate angle for radiative transfer from the inductance 22 to the leg of the loop 54. Although it is optimal to place the card at this angle for the most efficient transmission,
For example, when worn on the horse's ears or on the side of the head, the device operates with somewhat less efficiency.

As shown in FIG. 4, the underground loop 54 is illustrated as an oval. The signal generated on the coaxial cable 62 is shown by a graph line 73 where substantially zero or a small signal appears on the coaxial cable 62 when the transmitter card 18 enters the vertical space directly above the loop 54. . However, as soon as this threshold is passed, there is an extremely sharp increase in the input to loop 54. This continues in intensity until the card 18 passes the vertical line of the exit leg of the loop 54, after which a sharp decay in signal activity occurs as shown in FIG. The signal thus generated on the common coaxial line 62 has a square wave that appears just after the card passes the vertical plane of the entrance leg of the loop and ends just after it leaves the vertical plane above the exit leg of the loop. I understand.

Referring now to FIG. 8, coaxial cable 62 is connected directly to a plurality of receivers 75. 75A, 7
Each of these receivers, designated 5B, 75C, is primed and tuned to one frequency that matches the RF frequency output of a particular transmitting card 18. Thus, for example, receiver 75A is arranged to receive 360 KHz associated with a card having capacitor 51 arranged to provide a 360 KHz output. Receiver 75B is tuned to receive the 370 KHz frequency for use only in conjunction with a card 18 that has capacitor 51 selected to provide a 370 KHz output. In series with the coaxial cable 62 are a high frequency filter 80 and an amplifier 8.
1. The high frequency filter 80 is of conventional design and is arranged to attenuate all RF energy above the frequency range in which the system is designed to operate. Therefore, for example,
If this system is within or near 350KHz
The high frequency filter 80 is designed to attenuate all RF energy above approximately 350 KHz. By operating in this low frequency range and attenuating all frequencies above the 350KHz limit, a large amount of artificial or natural spurious radiation is removed.
The output from amplifier 81 is then transmitted to each receiver 7.
5. To compensate for loops having different sensitivities, it is desirable to include a controlled attenuator 82 to reduce the signal level for each receiver. This attenuator 82 equalizes the signal level to each receiver.

Each of the receivers 75 uses a phase-locked loop detection system that is necessary to identify frequencies other than the particular frequency that the receiver is programmed to use. This phase-locked loop system is common in the prior art and is illustrated on pages 199 to 224 of the "Signetis Linear" Volume 1 data book, which includes a phase detector and comparator 83, a filter 84
and a variable frequency oscillator (VCO) 85, in which tuning of the oscillator to the particular frequency of use is accomplished by manual adjustment at 86. In this system only, a signal with a frequency sufficiently equal to the variable frequency oscillator to maintain a phase-locked loop will generate one output from the system. This means of identification thus provides confirmation of the identity of the signal at selected frequencies only. This signal is then passed through a multiplier synchronization detector 87 and received and then amplified by an amplifier 88 and clipped by a clipper 89 to provide an essentially square wave output which is then transmitted. It is a square wave having the modulation frequency of the free-running oscillator 31 of the device card 18. Sound quality demodulator phase-locked loop demodulator 90 is referenced earlier.
It is arranged to identify all signals other than those of a predetermined selected audio frequency, such as a 1 KHz modulation.
This phase-locked circuit is similar to the phase-locked circuit used in the RF section described above and is described on pages 229 to 238 of the Sound Quality Detector Phase-Locked Loop in the Signetis Linear Volume 1 data book. and includes a low frequency phase comparator 91, a filter 92 and a crystal controlled oscillator (CCO) 93.

The crystal controlled oscillator 93 is connected to each receiver 75A, 75
It is clear that for some applications, where different discrimination between competitors is desired, although tuned for B etc. and having the same frequency, a separate audio frequency for each competitor may be used. Crystal controlled oscillator 93
This output from is then detected by a quadrature detector 95, which is amplified at 96 to provide a pulsed output for use within the timing system described below. It can be seen that in this receiver system, filter 80 attenuates all signals above the operating range of the system. The high discrimination of phase-locked RF systems rejects all signals except those within the precise range of the desired frequency, and only signals within these precise ranges that are modulated by the appropriate audio frequency are used. .
By this means the authenticity of this signal to the timer is guaranteed.

Referring now to FIGS. 6, 9 and 10, it can be seen that each of the separate receivers is capable of outputting a signal to the receiver bus logic 120 through this dual phase locked loop circuit. It is important that such signals are generated at different times. This signal is therefore sent to the one shot multi 112 shown in FIG. Typically, this signal is received at input 111 of NOR gate 113. A conventional one-shot multi-circuit is connected to a NAND gate 114 via a capacitor 115. This capacitor 115 determines the pulse width of the one shot multi 112 and sends each receiver separate signal to the receiver bus logic 120.

Receiver bus logic 120 routes this signal from each receiver to two separate sources. The first of these sources is a 16 to 4 line encoder 122. This line encoder 122
is conventionally connected to an encoder matrix with outputs through four separate NAND gates,
This encoder generates a separate 4-bit identification for each receiver 75A-75P.

A 16-to-4 line encoder 122 has its output connected to energize a 16-to-1 multiplexer 124. That is, once this line encoder 122 receives an identification of the identity of one receiver (and one transmitter passing through the loop) triggered 16
Pair-to-one multiplexer 124 is inherently activated. This multiplexer 124 is connected to the interrupt signal 12
6, and this signal 126 then passes to the computer circuitry shown in FIG.

Typically, the computer's interrupt circuitry causes the scan to occur instantaneously. A description of this scanning is provided below.

16-to-4 line encoder 122 sends this 4-bit identification output to 4-bit identification latch 130. The function of this 4-bit identification latch 130 is to store the identification of one triggered receiver. This accumulated identification is then provided to a random access memory along with sequential time information. Note that this identification information is used more than once. For example, as described in more detail below, this identification information is used to tag the minute information when it is first sent to the storage latch. After that, this identification information is divided into ten-second information, second information, and one-tenth information.
Label seconds information and 1/100th of a second information. This sequentially marked information is provided to random access memory for conventional recall when readout of race results is desired.

Referring briefly to FIG. 10, the oscillating crystal 140
has one output 142 that feeds directly to a time decimal counter 144. Referring principally to FIG. 9, the time decimal counter 144 includes a group of serially connected divider circuits which, with a suitable counter, start at 1×10 ^-5 seconds and begin at 1×10 ^{-4 seconds} .
seconds, 1×10 ^-3 seconds, 1×10 ^-2 seconds, 1×10 ^-1 seconds, 1
Divide into seconds, 10 seconds and 1 minute. All these counters are identical except for the 1/6 divider connected to the 10 second position, so the pulses from the clock are easily converted to minutes.

The output of each time decimal counter is a four bit information logic which is further sent to each storage latch 148. Each storage latch (SL)
Each is identified separately by a number from SL1 for 10 seconds to SL8 for 1×10 ^-5 seconds.

Time selection encoders 150 trigger respective storage latches 148. The reception of signals by time selection encoder 150 from input 152 is discussed below. Once the signal is on the time selection encoder 15
If received at 0, it sends an output via output 154 to freeze the respective latch. At the same time, the output 155 is sequentially activated to read out the accumulated time information. Output 155 is a 4-bit bus 1
It leads to 57. The 4-bit bus 157 first transfers the 4-bit information to the storage latch 1.
bit time latch 160. The remaining storage latches are then fed sequentially as described below. The sequence of transfers for each 4-bit time latch is summarized. Specifically, each time information consists of 8 bits. Four of these eight bits come from the four bit identification latch. The remaining 4 bits of these 8 bits are time information and come from the appropriate 4 bit time latches.

In the sequence, this 4-bit identification information and 4-bit time information move the entries marked with that identification information. The 4-bit bus 157 then indexes to transfer the 10 second storage latch 2 along with its 4-bit identification information. This process is repeated. followed by 4 bits of information, 4
Bit 1×10 ^-1 seconds information and 4 bits 1×10 ^-2 seconds information are all transferred. The time value, each time expressed as a 4-bit number, is marked with an entity identification value. This information is sequentially transferred to a random access memory where it is later recalled by conventional read techniques.

Output ends at an interval of 1×10 ^-2 seconds. Therefore, the remaining registers of 1×10 ⁻³ seconds, 1×10 ⁻⁴ seconds, and 1×10 ⁻⁵ seconds are not used. Rather, these registers are used to distinguish between closely spaced entities that pass through the same mark at substantially the same spacing. It can be seen that since the readout carried out here is shorter than 1×10 ^-5 seconds, the simultaneous recording of two entities passing through a constant loop is practically excluded. Conventional circuits start the clock such as clock start input 165. A reset 166 for storage latch 148 is provided to clear the storage latch with the most recent recorded time.

It is an important feature of the invention that the time information generated occurs only through real world events. That is, in the case of horse racing, this time information is generated only by transmitters passing through loops placed at continuous intervals around the race course.
This time information obtained by the circuit of the invention is therefore reliable. It is impossible to feed false information into this system. The contents of the random access memory loaded with the time input bits are thus safely stored. This is especially important in races where bets are placed, especially those involving handicap.

Having described time recording above, the computer circuitry will now be described. First, all parts of the computer are explained along with their inputs. Second
Here is a quick reference to the states that the computer goes through. Finally, an example of recording a specific time interval is given.

Referring to FIG. 10, a computer for use with the present invention is illustrated. For details,
The 4 MHz clock 140 provides its output to a two-phase divider clock 180. Two-phase divided clock 180 has a total output of 500 MHz. This clock 180 has two separate outputs 180,183. Each of these outputs communicates with central processing unit 185 and phase decoder 187. The central processing unit 185 described here is a standard product, such as Intel's 8008.

Focusing on the signal output by the two-phase divided clock 180, the central processing unit 185
contains four separate signals for each state of . These signals are output by phase decoder 187 and identified in order as φ ₁₁ , φ ₁₂ , φ ₁₃ and φ ₁₄ . All of these phases are passed for any given state of the central processing unit.

Central processing unit 185 includes state decoder 19
Outputs 3-bit logic to 0. status decoder 19
0 advances to different possible states for control logic 195. These states are, in order, T1, T2,
T3, T4, T5, interrupt state (T1i), stop state (STP) and standby state (HLT). As can be seen, all eight states are possible and communicated through control logic 195.

Read-write communications 196 are made to memory 200. Memory 200 is shown to include three sections. The first part is the central processing unit 185
Read-only memory (ROM) that contains programmed instructions for This portion of memory 200 is a section addressed to the computer for performing separate steps within its program. As explained below, this memory 200
A portion of the data is addressed in terms of commands for the computer to tune itself to receiving data.

Data is then received into a second portion of this memory 200, which is random access memory (RAM). Typically, the data received is a time portion of the entity at a particular detector station.

Furthermore, it is advantageous to provide a third part of this RAM with list data. For example, the horse's name, owner, trainer and jockey, and other relevant listings.
Data is provided to such a memory for use in the present invention.

As will be understood by those skilled in the art, reading of this memory is performed with respect to this data. Typically, data goes from memory 200 to input port 205. At this input port 205, memory data such as separate instructions are sent to the central processing unit 18 via an output 206 and via a data bus 210.
5 for processing. In this program, the L (Low) address register 21
2 and an H (High) address register 214. During each state of the computer, these address registers broadly operate on two separate functions.

First of all, these address registers are
Addresses memory or is part of an I/O instruction. In the latter case, the first two bytes of information (one byte to the L address register and the other byte to the H address register) will communicate instructions for the various components of the computer, word for word. .

When either memory is addressed or the computer is connected to either an input or output receiving state, the L address register 212 and the H address register 214 then store the information in the second can accept bytes. These bytes of information input a byte of data into memory, retrieve an instruction byte from memory, or output a byte of data.

Focusing on this second byte of data, the L address register contains the data for that byte that the machine desires to input, fetch, or output. The H address register is imperative. That is, instructions are moved within that register and within 8 bits to manipulate a particular byte of information.

The last two bits of the H address register are sent to cycle decoder 216. This cycle decoder 216 determines the appropriate cycle to be used. These cycles are further divided into instruction byte cycles (PCI), input/output cycles (PCC),
Feedback is provided to the control logic to provide memory write cycles (PCW) and memory read cycles (PCR).

Cycle decoder 216 is connected to control logic 19
5 to direct a particular sequence of states through which the central processing unit progresses.

An output port 220 is provided. This output is typically communicated to an output port multiplexer. Examples of outputs addressed through this output port 220 may include teletypes and numeric displays. A time selection port 152 is included within output port 220 as an important port for the purposes of the instructions that follow here. It is this output 15 that freezes the storage latch upon proper detection of an entity crossing the detection loop with each transmitter 23.
It is 2.

Input port 205 receives input 2 from memory 200
It turns out that it contains 25. Also, this input port 20
5 includes an 8-bit bus from two 4-bit latches 130,160. As previously mentioned, each of these latches has a 4-bit identification latch 130 and a 4-bit identification latch 130.
Time latch 160.

Having described the generally illustrated embodiment of the central processing unit according to the present invention, the timing will now be briefly explained. Timing is controlled via synchronization connection 230. Each cycle of synchronization consists of two φ
₁ pulse and two φ ₂ pulses, and is called a state. Each state thus includes four consecutive pulses as described below. Each of these states includes three parallel bits to status lines S0, S1 and S2.

A brief reference to the instruction fetch cycle (PCI), input/output cycle (PCC), and memory write cycle (PCW) with respect to computer timing.

During instruction fetch cycles, the processor typically receives input from an external control such as a teletype via bus 234. This data is transferred via bus 206 to bus 210 and bidirectional bus 211.
sent to. On bus 211 the serial information from the teletype is placed, for example, in parallel and then output in sequence first to the L address register and then to the H address register, each of these registers each containing 8 bit information. receive.

These outputs typically include memory addresses within ROM. In this sequence, this address typically results in an input/output cycle. That is, each logic state within the computer is matched for either inputting specific information or outputting specific information.

When the machine is in its desired state, either a memory write cycle (PCW) or a memory read cycle (PCR) is performed. Typically, L address register 212 during state T1.
is addressed by memory row information. state T2
Medium H address register 214 is addressed with memory page information. Once the memory is activated with the appropriate row and page, a memory read or write occurs within the RAM portion of memory 200 at state T3. Typically, the 8 bits contained within the L address register contain this information and the 8 bits within the H address register contain the execution instruction with the particular desired cycle format. The key to this acquisition of timing data is interrupt input 240. This interrupt input is routed through state decoder 190 to central processing unit 18 via associated logic.
5 to state T1i (interrupt state). This interrupt condition causes control logic 195 to terminate a particular microinstruction, remind central processing unit 185 of its location within a particular routine, and record timing information. This recording of timing information is triggered first by a command fetch cycle (PCI), then by an input/output cycle (PCC) that places the machine in the input state, and finally by a memory write cycle (PCW). Tracking of such instructions throughout the system is helpful with special reference to FIGS. 9 and 10.

From the explanation in Figure 5, the 16-to-1 multiplexer 12
4 was asserted with the output from the 16-to-4 line encoder 122, an interrupt signal 126 was generated. This interrupt signal 126 is connected to the interrupt signal input 24.
0 to central processing unit 185. At this time, central processing unit 185 completes any one of the remaining six cycles and then transitions to state T1i rather than state T1. During this time,
A suitable exit circuit interrupts the reset vector on that data line. During state T3,
The program counter stack is pushed down to one level. In this manner, the machine returns to the instruction at appropriate instruction intervals after the interrupt call is actually made while in the process of executing another instruction.

Interrupt signals trigger instruction fetch cycles (PCI). Assuming that horse 4 crosses a particular gate, receiver 75D outputs the appropriate signal via its one shot multi. Upon receipt of an interrupt signal, an instruction fetch cycle for output to time selection encoder 150 begins. Specifically, in states T1 and T2 the appropriate portions of memory are addressed with specific row and page instructions. A single instruction is retrieved from the appropriate portion of this memory.

This instruction places the machine in the desired output state. Typically, this desired output state is for output at 152 of output port 220. This is the signal that freezes each storage latch at the desired time interval. The memory data regarding this output state is
along bus 210 from memory 200 to central processing unit 185 and then to each L address register 212 in separate 8-bit serial bytes.
and proceeds to H address register 214. The time selection signal is output from output port 152.

The next instruction fetch cycle places the computer in the input state. This input state is for accepting and recording data.

As previously discussed, time select signal 152 freezes the storage latch. At the same time, 155 and 156
The output via energizes two respective 4-bit latches (i.e., 4-bit identification latch 130 and 4-bit time latch 160) and transmits their respective values to input port 205 via an 8-bit bus. let Indexing occurs as described above with the first read minute latch and then the 1×10 ^-2 second latch. Typically, the machine cycles so that it can receive input at input port 205 from two 4-bit latches. Connections to central processing unit 185 typically include buses 206 and 21.
0 and bidirectional bus 211.

A memory write cycle (PCW) is executed next. During state T1, L address register 212
receives a row address. During state T2, H address register 214 receives the page address. situation
During T3, memory data is addressed to the RAM portion of memory 200.

Reads are cascaded down through each latch. Each time an information bit is recorded. Identification information and time latch information are recorded serially in RAM. This read process continues until the 1x10 ^-2 second register latch is read. At this time, the central processing unit 18
5 does one of two things. It either goes to a halt state or continues with the interrupted sequence.

While recording race data, central processing unit 1
It turns out that it is desirable that 85 not be placed in the output state. The reason is that the information recorded by this device is property. However, this does not mean that they will be released until after the race is over.

The preferred programming disables this release of information during an ongoing race.

Once the RAM is loaded with time information from a single entity, reading is performed in a conventional manner. For example, a retrieval command may be input to input port 205 via bus 234 through a control unit such as a teletype. This serial information goes to the central processing unit and is converted into parallel bits for ROM instruction fetching. To fetch this instruction, first of all, the L address register 21 for output data is
2 and H address registers 214 to arrange the individual buses within control logic 195. This memory is then specially addressed and the data is output in serial form.

It is conventional to produce output data in a variety of formats. For example, a sequential part occurs along with a time part of a group of entities, such as a racetrack. Alternatively, the memory can be addressed and tested to accurately read a particular entity's time around the race track. For example, assuming the detectors were placed on the Farron bars, horse 4's time on each Farron bar would be printed on a piece of paper.
be outed. Moreover, once the time information
Stored serially in RAM, various read cycles are performed for each station for each entity, all of which are well known to those skilled in the art.

The above describes a device and process for recording race data. As for the process, the steps include freezing the time information and serially recording the time information in RAM. This serial recording occurs only in response to real-world events. It is not possible to enter time information in any circuit other than this published circuit that has the disclosed device. Therefore, the race can be held safely and reliably.

[Brief explanation of the drawing]

FIG. 1 is a schematic of a portion of a race track showing an underground transmitter detection loop. FIG. 2 is a diagram of a horse passing over this loop. FIG. 3 shows a transmitter that is typically worn on the horse's forehead.
FIG. 4 shows the waveform detected by the loop while the horse is passing over it. FIG. 5 is a block diagram of a transmitter worn on the forehead of a horse. FIG. 6 shows the circuit of this transmitter. FIG. 7 is a block diagram of a dual phase locked loop piston for receiving signals from a transmitter and blocking extraneous signals. FIG. 8 is a circuit diagram showing a typical one-shot multi used to receive separate signals from each station. 9th
The figure is a circuit diagram showing a circuit for inputting time information to this device. and FIG. 10 are circuit diagrams illustrating representative computer circuits that may be used to process received information. [Explanation of symbols], 18: Card, 19: Battery, 2
1: Electric circuit element, 22: Printed spiral loop, 2
3: Bag, 25: Forehead, 28: Horse.

Claims (1)

[Scope of Claims] 1. A method for indicating elapsed time from a starting point for each of a plurality of entities to a series of stations along a travel path of the entity, comprising: (a) each of the entities; (b) providing radio frequency transmitting means carried by said stations, each of said means emitting a separate radio frequency signal for each said entity; (c) providing radio frequency receiving means, each adapted to receive a periodic signal from said transmitting means when said transmitting means carried by an object is within the reception area of said station; (c) said receiving means; providing a plurality of detector means connected to said detector means, each of said detector means being adapted to identify and detect a selected one of said separate radio frequency signals; (d) detecting the signals and generating an output signal when signals at intervals from corresponding separate radio frequency signals are received by said radio frequency receiving means; (e) corresponding to each said entity; (f) providing a timing counter connected to each of said detector means; (g) a clock counter for said timing counter operable by said output signal; providing a time counter latch means, thereby accumulating a count in said time counter latch means when actually energized; (h) receiving a clock count from said time counter latch means and said marking means; emitting simultaneously a signal in the form of a binary word having said count and an entity indicator having said count; at least each said binary word is indicative of an elapsed time from said start of said each entity when an interval of radio frequency signals is received at each of said series of predetermined stations; The method comprises the step of retrieving the binary word from the storage means in response to a request signal. 2. In the method according to claim 1, there is provided time counter latch means for recording each digit of time information, and each digit of time information is sequentially marked, and each entity at each said station is A method for indicating elapsed time, characterized in that it includes the step of: sequentially storing each digit of time information and each indicator for a series of consecutive digits having the same indicator to record the time of a given time. 3. A device that indicates the elapsed time from a starting point for each of a plurality of entities to a series of stations along the travel path of all of the entities, the device: (b) radio frequency transmitting means carried by said station, each of said means emitting a separate radio frequency signal for each entity; (c) radio frequency receiving means connected to said receiving means, each adapted to receive a signal at intervals from said transmitting means when said transmitting means is within the reception area of each said station; a plurality of detector means, each of said means being adapted to identify and detect a selected one of said separate radio frequency signals; (d) said corresponding separate radio frequency signal; (e) actuating means associated with each of said detector means configured and arranged to generate an output signal when an interval signal from a frequency signal is received; (e) each said actuating means connected to each said actuating means; marking means for generating a binary indicator word identifying said output signal corresponding to an entity; (f) a timing counter connected to each of said detector means; (g) for operating said timing counter. (h) start means for connecting said clock means to said time counter for starting said time counter; (i) clock means operable to control said elapsed time when actually actuated by said time counter latching means; said timing counter latching means for said timing counter actuable by said output signal for accumulating a binary counter representing said counts; random access memory means coupled to the timing counter latch means; and (i) in response to the output signal, transmitting each of the indicators and each of the counts to the random access memory; control means for storing as multi-bit data words in a random access memory, whereby at least each interval of said separate radio frequency signals is received at each of said series of predetermined stations; said multi-bit data word indicating an elapsed time from said start of each said entity. 4. In the device according to claim 3,
Elapsed time, characterized in that the time counter and the time counter latch means include a separate counter for each digit of time information recorded and a separate latch for each digit of time recorded. A device that indicates 5. In the device according to claim 3,
Apparatus for indicating elapsed time, wherein said control means includes selection means for obtaining selected portions of said count and combining each said selected portion with said indicator into said multi-bit data word. 6. In the device according to claim 3,
The control means includes output means for retrieving the multi-bit data word from the random access memory and transmitting the data word to the display device upon receipt of a request signal from the display device. , a device that indicates elapsed time.