JPS6141051B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tape recorder, and its purpose is to reduce the number of operation command switches related to tape running operation and improve operability. The purpose is to reduce the number of lines connecting the operation command switch parts.

Traditional tape recorders allow fast forwarding, rewinding,
Since operation command switches are provided for each operation mode, such as constant feed and stop, each operation must be performed by selecting a switch, which is relatively troublesome, and also reduces the size of the tape recorder. However, if there are a large number of operation command switches, it is difficult to reduce the area occupied by them as desired. Moreover, when attempting to operate using remote control, the more operation command switches there are, the more lines will be required to connect the tape recorder itself and the operation command switches.
It was necessary to prepare a large-diameter, multi-conductor cord for the remote control, which obstructed the free movement of the operation command switch section.

The present invention is intended to eliminate such conventional drawbacks, and one embodiment thereof will be described below. First, in FIG. 1, 1 is a fast forward command switch, 2 is a rewind command switch, 3 is a play/stop command switch, 4 is a fast forward command storage circuit, 5 is a rewind command storage circuit, 6 is a play command storage circuit,
7 is a stop command storage circuit; 8 and 9 are delay circuits connected to the Q output terminals of the fast forward command storage circuit 4 and the rewind command circuit 5, respectively; and 10 is a logical sum of the two delay circuits 8 and 9. an OR circuit; 11 is an AND circuit that takes the AND of the output of the OR circuit 10 and the output of the play/stop command switch 3;
Reference numeral 12 denotes a delay circuit connected to the Q output terminal of the play command storage circuit 6, and reference numeral 13 denotes an AND circuit that performs the logical product of the output of the delay circuit 12 and the output of the play/stop command switch 3. The fast forward command switch 1 is connected to the set input S of the fast forward command storage circuit 4, and is also connected to the reset input R of the other storage circuits 5 to 7, and the rewind command switch 2 is connected to the rewind command storage circuit 5. Set input S
and other memory circuits 4, 6, 7
is connected to the reset input R of the Further, the output terminal of the AND circuit 11 is connected to the set input of the play command storage circuit 6, and the other storage circuit 4,
The output terminal of the AND circuit 13 is connected to the set input S of the stop command storage circuit 7, and the output terminal of the AND circuit 13 is connected to the set input S of the stop command storage circuit 7.
It is connected to the reset input R of 6.

The four memory circuits 4 to 7 are constructed of flip-flop circuits, and their Q outputs are applied to respective tape drive circuits (not shown). Furthermore, in the memory circuits 4 to 7, when the set input S becomes "L", the Q output is inverted from "H" to "L", and when the reset input R becomes "L", the Q output changes from "L" to "H". It operates in such a way that it is reversed. Block 1 surrounded by a dotted line in Figure 1
Reference numeral 4 denotes a one-chip negative logic input, negative logic output integrated circuit, so-called IC, which combines the memory circuits 4 to 7 and their input side connections, and has fast forward command input terminals a,
Rewind command input terminal b, play command input terminal c,
It has four input terminals, a stop command input terminal d, and four output terminals: a fast forward command output terminal A, a rewind command output terminal B, a play command output terminal C, and a stop command output terminal D.

The circuit embodying the configuration shown in Fig. 1 is the second circuit.
This is the circuit shown in the figure, and the same components as in FIG. 1 are given the same numbers and detailed explanations will be omitted. In FIG. 2, the delay circuit 8 consists of a resistor 15 and a capacitor 16.
The delay circuit 9 is composed of a resistor 17 and a capacitor 18, and the delay circuit 12 is composed of a resistor 19 and a capacitor 20. 21 is delay circuit 1
2 and the NAND gate 13a, and constitutes the AND circuit 13 together with the NAND gate 13a. Further, a parallel circuit of a resistor 22 and a capacitor 23 interposed between the play/stop command switch 3 and the AND circuit 11 constitutes a differential circuit, which acts to generate a pulse only at the moment the switch 3 is turned on. . 24 is Nand Gate 1
This inverter constitutes the AND circuit 11 together with 1a.

The operation of the above embodiment will now be explained.
First, when you turn on fast-forward command switch 1, IC1
4's input terminal a becomes "L", and the output of IC14 is that terminal A becomes "L" and other terminals C to D become "H".
becomes. The tape drive circuit is controlled by the "L" output, and the tape recorder enters a fast forward operation state. Also, when rewind switch 2 is turned on, input terminal b of IC14 becomes "L", and IC1
4 output, terminal B becomes "L", and other terminals A,
C and D become "H". The L output causes the tape recorder to enter the rewind state. If this tape recorder is currently in fast forward mode, IC14
Since the output terminal A of
The output of the NAND gate (in the figure) 10 becomes "H". Further, even when the present tape recorder is in the rewinding state, the capacitor 18 of the delay circuit 9 is in a discharged state, so the output of the OR circuit 10 becomes "H". If this tape recorder is in the playing or stopped state,
Since output terminals A and B of the IC 14 are both "H", the output of the OR circuit 10 is "L". Therefore, when the play/stop command switch 3 is turned on when the present tape recorder is in the fast forward or rewind state, that is, when the output of the OR circuit 10 is "H", this "L" output is capacitor 2
2. It is differentiated by the resistor 23, and an "H" pulse is generated for a short time at the output of the inverter 24. When the output "H" of the above-mentioned OR circuit 10 and the "H" output pulse of the inverter 24 are input to the AND circuit 12, an "L" pulse appears on the output side, and this "L" pulse , are input to the input terminal c of the IC14. As a result, the output terminal C of IC14 becomes "L", and the other output terminals A, B, D
becomes "L", and the tape recorder enters the play state. At this time, the output terminals A and B of the IC 14 both become "H", but because of the delay circuits 8 and 9, the output of the OR circuit 10 does not become "L" immediately and remains "H" for a while. The output of the AND circuit 11 becomes "L" while the inverter 24 outputs a "H" pulse, and a pulse with a pulse width sufficient to completely change the state of the IC 14 is output from the IC 14. is applied to input terminal c of or,
Similarly, the delay circuit 12 holds the previous state for a time longer than the output pulse width of the inverter 24, so the output of the inverter 21 remains "L", and the output of the AND circuit 13 remains "H". It remains unchanged.

On the other hand, if the play/stop command switch 3 is turned on while this tape recorder is in the play state, the IC
Since the output terminals A and B of 14 are both "H", the output of the OR circuit 10 is "L". Therefore, the output of the AND circuit 11 remains at "H" and does not change. On the other hand, since the output terminal C of the IC 14 is "L", the output of the inverter 21 is "H", and the "H" pulse of the output of the inverter 24 causes the output of the AND circuit 13 to have a "L" pulse. appears and is applied to the input terminal d of the IC 14, causing the tape recorder to stop.

In this way, in this embodiment, the fast forward command switch 1
When turned on, it enters the fast forward mode, when the rewind command switch 2 is turned on, it enters the rewind state, and when the play and stop command switch 3 is turned on during fast forward or rewind, it enters the play state, and when the play and stop command is turned on during play, it enters the play state. When switch 3 is turned on, the machine is stopped. That is, four tape running modes can be controlled by three operation command switches.

As explained above, the tape recorder of the present invention allows a plurality of operation modes to be performed using fewer operation command switches than the number of modes, so it is possible to improve operability and save space for operation. This makes it easier to downsize the tape recorder, and also allows the wire connecting the tape recorder body and the operation command switch section to be smaller in diameter during remote control, allowing the operation section to be moved freely. It becomes like this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a tape recorder according to an embodiment of the present invention, and FIG. 2 is a circuit diagram thereof. 1...Fast forward command switch, 2...Rewind command switch, 3...Play and stop command switch, 4
...Fast forward command memory circuit, 5...Rewind command memory circuit, 6...Play command memory circuit, 7...Stop command memory circuit, 8, 9, 12...Delay circuit, 10...
...OR circuit, 11, 13...AND circuit.

Claims (1)

[Claims] 1 At least three operation command switches: a first operation command switch for fast forwarding, a second operation command switch for rewinding, a third operation command switch for constant speed forwarding and stopping, and a third operation command switch for fast forwarding command storage. at least four storage circuits: a first storage circuit, a second storage circuit for rewinding command storage, a third storage circuit for constant speed feed command storage, and a fourth storage circuit for stop command storage; 1, first and second delay circuits connected to the output terminals of the second storage circuit, respectively; a first logic circuit that ORs the outputs of the first and second delay circuits; a second logic circuit that takes an AND of the output of the first logic circuit and the output of the third operation command switch; a third delay circuit connected to the output terminal of the third storage circuit; a third logic circuit that takes an AND of the output of the third delay circuit and the output of the third operation command switch;
The output of the operation command switch is applied to the set input of the first memory circuit and the reset input of the other memory circuit, and the output of the second operation command switch is applied to the set input of the second memory circuit and the other memory circuit. In addition to the reset input of the circuit, the output of the second logic circuit is applied to the set input of the third memory circuit and the reset input of the other memory circuit, and the output of the third logic circuit is applied to the set input of the fourth memory circuit. and a tape recorder configured to be added to the reset input of other memory circuits.