JPS6141428B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a data transfer device.

In conventional data transfer equipment, when a failure occurs in the data buffer memory of a certain channel,
Operation of all channels is terminated, operation of only the channel when a failure occurs is terminated, or data transfer is retried only for that channel. Therefore, at least the channel in which the failure has occurred is stopped, and as a result, the channel becomes unusable, hindering efficient data transfer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer device that eliminates the above-mentioned drawbacks.

The device of the present invention includes a storage means in which a storage area is allocated corresponding to an input/output channel, a failure detection means for detecting a failure in information stored in the storage means, and a failure detection means for detecting a failure in the information. faulty address storage means for storing address information indicating a storage location of said storage means specified when said storage means is in use; and a comparison for comparing an address for accessing said storage means with an address stored in said faulty address storage means. and means for specifying an address for accessing a storage area of the storage means to which the input/output channel is not allocated when the comparison means finds a match. shall be.

Next, the present invention will be explained in detail with reference to the drawings. An embodiment of the present invention shown in FIG. 1 is comprised of a data buffer memory 1, registers 2, 3, and 5, a comparison circuit 4, a flip-flop 6, and a fault detection circuit 7. Data buffer memory 1 is a memory that temporarily stores data from the main memory to the input/output channel or from the input/output channel to the main memory, and is assigned to correspond to the input/output channel according to the contents of register 2, which stores the currently operating channel number. area is accessed. The fault detection circuit 7 is a circuit that constantly monitors the output of the data buffer memory 1 and detects a fault in the data buffer memory 1 based on whether there is any error in the output data. A fault in the data buffer memory 1 detected by the fault detection circuit 7 sets the flip-flop 6 to logic "1" via the signal line 101,
Indicates that a failure has occurred. At the same time, signal line 101
The channel number of register 2 given through is set to register 3. This register 3
is a register that stores the channel number when a failure occurs.

Next, the input/output channel that detected the failure will retry the data transfer, etc., based on the channel number.
When the data buffer memory 1 is accessed again, the register 2 that attempts to access the data buffer memory 1
The comparison circuit 4 compares the channel number of the register 3 with the faulty channel number of the register 3 to see if they match. The comparison result is determined by the gate circuit 11 when the logic "1" is set in the flip-flop 6.
If a failure has occurred, the validity is determined via the switching signal of the gate circuits 12 and 13, that is, the switching signal of the register 2 or the register 5 that stores the address of the unused area of the data buffer memory 1. This is a signal for switching between specifying an address in the data buffer memory 1. If a failure has occurred, the address of the unused area of the register 5 is output, the unused area of the data buffer memory 1 is accessed, and the unused area is essentially transferred to the data buffer memory of the channel. 1.

FIG. 2 is a diagram showing the internal structure of the data buffer memory 1, which is composed of areas CH0 to CHn with channel numbers 0 to n and an unused area, where reference numeral E is a substitute for a failed input/output channel. means area.

The present invention is based on the premise that there is an unused area in the data buffer memory 1, but in recent years, memory elements have been increasingly integrated into LSIs and integrated in the word direction. Furthermore, the number of input/output channels is physically limited. Therefore, when a memory element is used in a data buffer memory as in this embodiment, it is naturally expected that an unused area will appear.

As described above, the present invention can be implemented without adding an unused area or a new memory element, but if the emphasis is on reliability, the effect of the present invention can be achieved even if a new memory element is added. can get.

As can be seen from the above explanation, there is no effect on input/output channels other than the input/output channel in which the failure has occurred. Furthermore, the input/output channel in which the failure has occurred can continue to perform input/output operations after retrying. For this reason, continuity of equipment operation is maintained, and the average failure-free time is 22 when considering only data buffer memory.
Double.

The present invention improves reliability by isolating a fault in the data buffer memory of one channel and replacing it with an unused area without affecting other channels, and also frees up LSI memory elements. This has the effect of achieving effective utilization of the usage area.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
1 is a diagram showing the internal configuration of the data buffer memory shown in FIG. 1. 1 and 2, 1...data buffer memory, 2...channel number register, 3
... Failure channel number register, 4 ... Comparison circuit, 5 ... Unused area address register, 6 ...
Fault occurrence storage flip-flop, 7...fault detection circuit, 11, 12, 13... switching gate circuit.

Claims (1)

[Scope of Claims] 1. Storage means having storage areas allocated corresponding to input/output channels; Failure detection means for detecting failures in information stored in the storage means; and Failure detection means for detecting failures in the information by the failure detection means. A faulty address storage means for storing address information indicating a storage location of the storage means designated at the time of detection; and comparing an address for accessing the storage means with an address stored in the faulty address storage means. Comparing means; and means for specifying an address for accessing a storage area of the storage means to which the input/output channel is not allocated when a match is found by the comparison means. Characteristic data transfer device.