JPS6141430B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a communication control device that transmits and receives data under the control of a program of a host device, and particularly relates to an improvement in reception processing of the communication control device. Generally speaking, transmission control procedures (communication regulations) agreed upon between data senders and receivers when performing data communication.
Depending on the received character, a response monitoring code consisting of one character, a response monitoring sequence consisting of a plurality of character strings,
They can be classified into information block start characters, information blocks consisting of multiple character strings following the information block start characters, information block end characters, and general characters that have no meaning on their own. Further, in the transmission control procedure, a plurality of communication phases are defined, and valid received characters and received character strings are defined for each communication phase. In this way, the definition of response monitoring characters or response monitoring sequences differs depending on the transmission control procedure, and even if the transmission control procedure is the same, valid reception characters and character strings differ depending on the communication phase. The control device transferred the received characters as they were to the higher-level device and issued an interrupt, and the program on the higher-level device side determined the validity of the received characters based on the received characters and the communication phase at that time. Furthermore, the program determines whether or not the received character is part of a response monitoring sequence consisting of a plurality of character strings based on a combination with a previously received character string. With this conventional communication control device, it is necessary to interrupt the host device every time one character of data is received, and even if the character is invalid in the current communication phase, it must be transferred to the host device. The load on the device is heavy, and the host device determines the received character and communication phase to create a jump address for the branch instruction of the interrupt processing routine, so the program returns to the processing routine of the transmission control procedure after reception. It takes a considerable amount of time to proceed, which is one of the factors that hinders the improvement of processing performance when processing high-speed lines or multiple lines. In addition, in order to solve this problem, if the received characters and received character strings are determined on the communication control device side, a plurality of receive buffer registers for determining a response monitoring sequence consisting of a plurality of character strings,
A control circuit to sequentially store received characters in these multiple registers and a circuit to decode the received characters are required, and changing the response monitoring code to be decoded due to changes in the transmission control procedure requires a circuit. There were drawbacks such as the need for changes. The present invention is an improvement on this, and an object of the present invention is to provide a communication control device that can reduce the number of interruptions to a host device and can flexibly respond to changes in transmission control procedures. The present invention provides determination of received characters and received character strings,
and determines the validity of the received character and received character string in the communication phase at that time, interrupts the host device only if the received character is a valid character, and transfers the received character determination result to the host device. , the burden on the host device is reduced by reducing the number of interrupts to the host device in charge of transmission control and the number of transfers of received characters, and by eliminating unnecessary processing for determining received characters and received character strings in the host device, It also determines the validity of the above-mentioned received characters and received character strings, the necessity of an interrupt, the received character that caused the interrupt, the interrupt factor that characterizes the received character string, and the validity of the next received character. To provide a communication control device that can easily cope with changes in transmission control procedures by defining change information of reception status for transmission as a control word and rewriting this control word. The present invention provides a buffer register that stores only one received character, a reception status storage register that stores a reception status determined by a communication phase and a previously received character string, information for changing the reception status, and a buffer register that stores only one received character. a control word storage register that stores a plurality of control words consisting of whether or not to interrupt the device, and when interrupting, the received character that caused the interrupt and interrupt information that characterizes the received character string; , a control word storage address creation circuit for reading out a control word based on a combination of a reception state and a received character, and changing the reception state according to the read control word, Requests an interrupt to the higher-level device according to the control word, and
The present invention is characterized in that it is configured to transfer an interrupt factor to a host device in accordance with the read control word. According to the control word read from the control word storage register, the receiving state is changed, an interrupt is requested to the host device, and the interrupt cause is transferred to the host device. An interrupt is not made to the host device by the interrupt signal bit of the control word read with the received character and the address created in the receiving state. Therefore, even if there is a change in the transmission control procedure, it can be handled by simply changing the contents of the control word storage register, such as the definition of the reception control code and the transition of the communication phase. Furthermore, since no interrupt is made to the host device depending on the interrupt signal bit of the control word, the burden on the host device can be reduced. Next, embodiments of the present invention will be described in detail based on the drawings. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a transmission control code storage register that stores a transmission control code to be detected sent from a host device through a signal line group 100. The output of this transmission control code storage register 1 is:
It is connected to one input of the comparator circuit 2 by a signal line group 101. The signal line group 100 is also used to rewrite the contents of the transmission control code storage register 1 as necessary. 3 is a transmission control code storage address register, and transmission control code storage register 1
Give the address to read. The output of the transmission control code storage address register 3 is connected to the address input of the transmission control code storage register 1 and the input of the control word address generation circuit 4 by a signal line group 102. Further, the input of the transmission control code storage address register 3 is connected to the signal line group 103 which is the output of the comparison circuit 2. 5 is a receive buffer register which stores one received character. The output of this reception buffer register 5 is connected to another input of the comparator circuit 2 by a signal line group 104. Reference numeral 6 denotes a reception status storage register, the output of which is connected to the input of the control word address generation circuit 4 through a signal line group 105. The output of the control word address generation circuit 4 is connected to the input of the control word storage register 7 by a signal line group 106. The signal line group 107 is used to write a control word into the control word storage register 7. Further, the output of the control word storage register 7 is connected to the input of the reception status storage register 6 through a signal line group 108 and to the input of the interrupt control circuit 8 through a signal line group 109. The output signal line 110 of the interrupt control circuit 8 is an interrupt request signal line for a host device, and the output signal line group 111 is also used to transfer an interrupt factor to the host device. With such a configuration, the received characters stored in the receive buffer register 5 via the signal line group 112 are
Transmission control code storage register 1 by comparison circuit 2
is compared with the contents of The initial value of the transmission control code storage address register 3 is (000), and is incremented by 1 until the received character and the output of the transmission control code storage register 1 match. If they match, the comparison circuit 2 stops the addition operation of the transmission control code storage address register 3 via the signal line 103. In addition, this addition operation is performed when the received character and the output of the transmission control code storage register 1 cannot match even if the value of the transmission control code address register 3 reaches (110).
The transmission control code address register 3 outputs the value (111) and stops. Table 1 shows transmission control code storage address register 3.
2 is a table showing an example of the correspondence between the output of the transmission control code storage register 1 and the output of the transmission control code storage register 1. The transmission control code storage address register 3 becomes an initial value (000) every time a received character is stored in the reception buffer register 5. Therefore, Table 1 shows that if the received character is (00000010), the transmission control

【table】

[Table] If the output of code address register 3 is (000) and the received character is (10000011), it will be (001), and if the received character does not match the contents of transmission control code storage register 1, it will be (111). It shows. On the other hand, the control word stored in the control word storage register 7 is read out according to the address created by the control word storage address creation circuit 4. FIG. 2 is a diagram showing the output of this control word storage address generation circuit 4. Table 2 shows the correspondence between these addresses and control words.

[Table] As shown in FIG. 2, the address consists of a bit group A0 and a bit group A1. In this embodiment, bit group A
0 corresponds to the output of the reception status storage register 6, and bit group A1 corresponds to the output of the transmission control code storage address register 3. Therefore, the contents of the address determined by the received character and reception state are read as the control word. FIG. 3 shows the control word storage register 7 shown in FIG.
It is a figure which shows the control word of. In FIG. 3, the control word consists of bit group B0, bit B1, and bit group B2. Bit group B0 of read control word
is stored in the reception status storage register 6. Bit B1 and bit group B2 are also supplied to interrupt control circuit 8. In this embodiment, the interrupt control circuit 8 issues an interrupt request to the host device when bit B1 is "1" and transfers the bit group B2 as an interrupt factor to the host device. If bit B1 is "0", no interrupt is issued to the host device. If the received character is (00000010), the output of the transmission control code storage address register 3 (bit group A1 of the control word storage address) is (000) as shown in Table 1.
If the output of the reception status storage register 6 (bit group A0 of the control word storage address) is (00), the control word (10100001) is read out as shown in Table 2. This control word (10100001) indicates to change the receiving state to (10), request an interrupt to the host device, and transfer the interrupt cause (00001). Similarly, if the received character is (10000011), when the reception status is (00), the control word (00000000)
, when the reception status is (10), the control word (00100010)
Read out. Therefore, the received character (10000011) is
This indicates that if the receiving state is (00), it is ignored, and if the receiving state is (10), an interrupt is generated to the host device to change the receiving state from (10) to (00). Therefore, when detecting a response monitoring sequence consisting of two characters, a control word is created so that when the start character of the sequence is received, the reception status is updated and no interrupt is generated. When the next received character matches the second character of the sequence,
If an interrupt is generated and a control word is created to distinguish the interrupt factor from other factors, only one interrupt is required for receiving a two-character sequence, and there is no need to transfer the received character to the host device. , there is no need to prepare as many reception buffer registers as there are character strings in order to determine the character strings. Note that when received characters and character strings are handled differently depending on the communication phase, and when a character that causes the communication phase to be updated is received, a control word is created to update the reception status. .
In addition, in a transmission control system with a large number of reception states, if you do not want to increase the number of control word storage registers 7 and reception state storage registers 6 too much, the contents of the control word storage registers 7 when changing the communication phase All you have to do is rewrite. Furthermore, the transmission control code storage register 1, transmission control code storage address register 3, and comparison circuit 2 shown in Figure 1 are for converting the received character (8 bits) into the lower 3 bits of the control word storage address. Yes, it is also possible to delete the control word by increasing the number of bits of the control word storage address, increasing the receiving state, and receiving characters (8 bits). If there is a change in the transmission control procedure, it can be handled by changing the contents of the control word storage register. As explained above, according to the present invention, an address is created based on received characters and a reception state, a control word prepared in advance is read using this address, and the reception state is changed or assigned according to this control word. It controls the generation of interrupt requests and the transfer of interrupt factors.
Only valid interrupts or transfers can be made to the host device, reducing the burden on the host device. This enables high-speed operation or multi-line processing. Further, when the control procedure is changed, the content of the control word can be simply changed without changing the hardware, so there is an excellent effect of being able to respond flexibly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. Second
The figure shows the output of the same control word storage address creation circuit. FIG. 3 is a diagram showing the output (control word) of the control word storage register. 1...Transmission control code storage register, 2...Comparison circuit, 3...Transmission control code storage address register, 4...Control word storage address creation circuit, 5...
Reception buffer register, 6... Reception status storage register, 7... Control word storage register, 8... Interrupt control circuit, 100, 101, 102, 104, 10
5,106,107,108,109,111,
112... Signal line group, 103, 110... Signal line.

Claims (1)

[Claims] 1. A communication control device that sends and receives data to and from a communication line under program control of a host device, comprising: a buffer register that stores only one received character; and a reception status storage that stores the reception status. a register, a control word storage register that stores a plurality of control words consisting of information for changing the reception state and information for controlling interrupts to the host device, and a control word storage register that stores the control words by a combination of the reception state and the received character. A control word storage address creation circuit for reading; a circuit that changes the receiving state according to the read control word; requests an interrupt to the host device according to the read control word; and 1. A communication control device comprising: control means for transferring an interrupt factor to a host device according to a control word.