JPS6142428B2 - - Google Patents
Info
- Publication number
- JPS6142428B2 JPS6142428B2 JP56047057A JP4705781A JPS6142428B2 JP S6142428 B2 JPS6142428 B2 JP S6142428B2 JP 56047057 A JP56047057 A JP 56047057A JP 4705781 A JP4705781 A JP 4705781A JP S6142428 B2 JPS6142428 B2 JP S6142428B2
- Authority
- JP
- Japan
- Prior art keywords
- resin part
- resin
- chip
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/18—Circuits for erasing optically
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は、光を照射することにより消去できる
EPROM（消去可能なPROM）のICチツプを樹脂
封止した半導体装置の新規な製造方法に関するも
のである。[Detailed description of the invention] The present invention can be erased by irradiating light.
This invention relates to a new method for manufacturing a semiconductor device in which an EPROM (erasable PROM) IC chip is sealed with resin.
一般にEPROMチツプは、外部からの光の照射
を受けることができるように、セラミツクのパツ
ケージ内に収容され照射用の窓が設けられたキヤ
ツプにより封止されている。その構造は周知であ
る。セラミツクパツケージは複数のセラミツク板
を積層する等その構造が複雑で、製造コストが高
くまた材料自体も高価なものである。特に最近半
導体チツプ自体のコストが低減され装置全体の価
格に対してセラミツクパツケージの価格の占める
割合が高くなつている。 Generally, an EPROM chip is housed in a ceramic package and sealed with a cap provided with a window for irradiation so that it can receive light from the outside. Its structure is well known. Ceramic packages have a complicated structure, such as laminating a plurality of ceramic plates, and are expensive to manufacture and the materials themselves are expensive. Particularly recently, as the cost of semiconductor chips themselves has been reduced, the cost of ceramic packages has become a larger proportion of the cost of the entire device.
本発明の目的は、EPROMチツプを収容する低
価格のパツケージとして、樹脂封止タイプの半導
体装置を預易に形成することができる製造方法を
提供することにある。本発明の特徴は、リードフ
レームに搭載されたICチツプの表面上に所定厚
さの第１の樹脂部を積み上げる工程と、該第１の
樹脂部上面が露出するよう該リードフレーム、該
ICチツプ及び該第１の樹脂部を第２の樹脂部で
被覆する工程と、該第１の樹脂部を除去し、該
ICチツプの表面を露出せしめるキヤビテイ部を
形成する工程と、光を透過するキヤツプ部材で該
キヤビテイ部を封止する工程とを有することにあ
る。 An object of the present invention is to provide a manufacturing method that can easily form a resin-sealed type semiconductor device as a low-cost package that accommodates an EPROM chip. The features of the present invention include a step of stacking a first resin part of a predetermined thickness on the surface of an IC chip mounted on a lead frame, and stacking the first resin part of the lead frame so that the upper surface of the first resin part is exposed.
A step of covering the IC chip and the first resin part with a second resin part, and removing the first resin part and covering the first resin part with a second resin part.
The method includes the steps of forming a cavity portion that exposes the surface of the IC chip, and sealing the cavity portion with a cap member that transmits light.
以下本発明の一実施例を図面に従つて詳細に説
明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第１図参照
リードフレーム１のチツプ搭載部１′上にICチ
ツプ２を従来の通常方法により搭載し、ICチツ
プ２の電極とリードフレーム１とを導通するワイ
ヤー３を形成する。その後ICチツプ２の表面に
まず薄く保護用樹脂層（図示せず）を形成し、さ
らに表面上に粘度の高い樹脂を積み上げ第１の樹
脂部４を形成する。Refer to FIG. 1. An IC chip 2 is mounted on a chip mounting portion 1' of a lead frame 1 by a conventional conventional method, and a wire 3 is formed to connect the electrodes of the IC chip 2 and the lead frame 1. Thereafter, a thin protective resin layer (not shown) is first formed on the surface of the IC chip 2, and then a highly viscous resin is piled up on the surface to form the first resin portion 4.
第２図参照
上記第１の樹脂部が固まつた後、通常のモール
ド法により第２の樹脂部５を形成し、ICチツプ
２、リードフレーム１、ワイヤー３及び第１の樹
脂部側面を封止する。この時第１の樹脂部４上面
は外部に露出させておく。See Figure 2 After the first resin part has hardened, a second resin part 5 is formed by a normal molding method, and the IC chip 2, lead frame 1, wire 3, and side surfaces of the first resin part are sealed. Stop. At this time, the upper surface of the first resin part 4 is exposed to the outside.
第３図参照
第１の樹脂部４は溶かし第２の樹脂部５は溶か
さない溶剤により、第１の樹脂部４を除去し、
ICチツプ２の表面を露出させるキヤビテイ部４
０形成する。See Figure 3. The first resin part 4 is removed using a solvent that does not dissolve the first resin part 4 but does not dissolve the second resin part 5.
Cavity part 4 that exposes the surface of IC chip 2
Form 0.
第４図参照
N2等の不活性ガス雰囲気中で、キヤビテイ部
４０の内部をキヤツプ材６により封止する。この
キヤツプ部材６は紫外線等の光を透過する部分を
有している。Refer to FIG. 4. The inside of the cavity 40 is sealed with a cap material 6 in an inert gas atmosphere such as N2 . This cap member 6 has a portion that transmits light such as ultraviolet rays.
以上説明した様に本発明によれば、従来の樹脂
封止タイプの半導体装置の製造工程に、単に第１
の樹脂部４を形成する工程、それを除去する工程
及びキヤツプ部材６を設ける工程を加えるだけで
よく、従来の製造工程を利用して簡単に行なうこ
とができる。そしてそのような簡単な工程で、従
来のセラミツクパツケージよりもはるかに低価格
にすることができる。 As explained above, according to the present invention, only the first step is added to the manufacturing process of a conventional resin-sealed type semiconductor device.
It is only necessary to add a step of forming the resin part 4, a step of removing it, and a step of providing the cap member 6, and it can be easily carried out using conventional manufacturing processes. And with such a simple process, the price can be much lower than that of conventional ceramic packages.
第１図乃至第４図は本発明の一実施例の各工程
を示す断面図である。
図中、１はリードフレーム、２はICチツプ、
３はワイヤー、４は第１の樹脂部、５は第２の樹
脂部、６はキヤツプ部材である。
1 to 4 are cross-sectional views showing each step of an embodiment of the present invention. In the figure, 1 is a lead frame, 2 is an IC chip,
3 is a wire, 4 is a first resin part, 5 is a second resin part, and 6 is a cap member.
Claims (1)
面上に所定厚さの第１の樹脂部を積み上げる工程
と、該第１の樹脂部上面が露出するよう該リード
フレーム、該ICチツプ及び該第１の樹脂部を第
２の樹脂部で被覆する工程と、該第１の樹脂部を
除去し、該ICチツプの表面を露出せしめるキヤ
ビテイ部を形成する工程と、光を透過するキヤツ
プ部材で該キヤビテイ部を封止する工程とを有す
ることを特徴とする樹脂封止型半導体装置の製造
方法。1. A step of stacking a first resin part of a predetermined thickness on the surface of an IC chip mounted on a lead frame, and stacking the lead frame, the IC chip, and the first resin part so that the top surface of the first resin part is exposed. a process of covering the resin part with a second resin part; a process of removing the first resin part to form a cavity part that exposes the surface of the IC chip; and a process of covering the cavity part with a light-transmitting cap member. 1. A method for manufacturing a resin-sealed semiconductor device, comprising the step of sealing a resin-sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56047057A JPS57162352A (en) | 1981-03-30 | 1981-03-30 | Manufacture of resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56047057A JPS57162352A (en) | 1981-03-30 | 1981-03-30 | Manufacture of resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57162352A JPS57162352A (en) | 1982-10-06 |
| JPS6142428B2 true JPS6142428B2 (en) | 1986-09-20 |
Family
ID=12764521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56047057A Granted JPS57162352A (en) | 1981-03-30 | 1981-03-30 | Manufacture of resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162352A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4766095A (en) * | 1985-01-04 | 1988-08-23 | Oki Electric Industry Co., Ltd. | Method of manufacturing eprom device |
| JPS61156249U (en) * | 1985-03-18 | 1986-09-27 | ||
| US5026667A (en) * | 1987-12-29 | 1991-06-25 | Analog Devices, Incorporated | Producing integrated circuit chips with reduced stress effects |
| US6165816A (en) * | 1996-06-13 | 2000-12-26 | Nikko Company | Fabrication of electronic components having a hollow package structure with a ceramic lid |
| KR101032337B1 (en) | 2002-12-13 | 2011-05-09 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Light emitting device and manufacturing method thereof |
| JP2009267272A (en) * | 2008-04-29 | 2009-11-12 | New Japan Radio Co Ltd | Semiconductor hollow package and method of manufacturing the same |
| JP2010062232A (en) * | 2008-09-02 | 2010-03-18 | Nec Electronics Corp | Method of manufacturing semiconductor device with element function part exposed |
-
1981
- 1981-03-30 JP JP56047057A patent/JPS57162352A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57162352A (en) | 1982-10-06 |
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