JPS6142803B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention converts an analog signal into a digital signal, selects a desired thermal head from a thermal head array using the digital signal, records it on thermal recording paper, and converts the original analog signal into a digital signal. Regarding thermal head arrays that draw signal waveforms on thermal recording paper, heating control is particularly required to prevent excessive temperature rises in the thermal heads due to continuous application of heating power to the same thermal head in the thermal head array. It is related to the device.

FIG. 1 is a block diagram showing an example of such a thermal head array, in which 1 is an analog signal input terminal, 2 is an amplifier, and 3 is an analog-to-digital converter (hereinafter referred to as AD converter). In AD converter 3, CLK is the clock input terminal.
At the sampling point indicated by _P15 (described in a later section), the input analog signal is converted into an 8-bit digital signal and output. These 8 bits are represented by a, b, . . . g, h in order from the lowest bit. 4 is a control circuit, 5 is a switch element group, and 6 is a thermal head array. In the example shown in the figure, there are 256 thermal heads made of resistors (indicated by (6000), ... (6255)).
It consists of an array of . 7 is a power source.

The surface of the paper in FIG. 1 corresponds to the surface of thermal recording paper (not shown), and the thermal head array 6 is placed on the recording paper and does not move, but the recording paper is fed in a direction perpendicular to the arrangement of the thermal heads. be done. If the binary 8-bit digital signals a,...h are decoded, they will be 0 to 255 (shown as (4000),...(4255) in Figure 1).
A 256-step signal is obtained, and this signal can be used to heat the corresponding thermal head via the switch element group 5 and record at that position. The amplitude of the analog signal at each sampling point is expressed in 256 steps from 0 to 255 by digital signals a,...h, and this is recorded as an amount proportional to the original analog signal depending on the array position of each thermal head. Therefore, recording can be performed in the same manner as when one thermal head is driven in the arrangement direction of the thermal head array 6 by an amount proportional to the amplitude of the analog signal while the thermal head array remains stationary. In this sense, a recording device using such a thermal head array is referred to as a stationary, thermal head, or recorder (Stationary thermal head).
Also called recorder.

Stationaries, thermal heads, and recorders have no moving parts other than constant paper feed, so they are suitable for recording phenomena that change at high speed, but they have the disadvantage that the thermal head has a large temperature time constant. In order to perform recording in response to control signal input, it is necessary to apply a sufficiently large heating power when the signal is input to rapidly raise the temperature of the thermal head, but in this case, the control signal is input continuously. If the temperature is exceeded, the temperature of the thermal head will rise excessively. In order to avoid such an excessive temperature rise, in the past, data was divided into odd-numbered heads and even-numbered heads, and if recording was performed by the odd-numbered heads in a time-division manner, then the even-numbered heads could be recorded without applying power to the odd-numbered heads. The design was such that heating power was not input continuously to the same head. Therefore, there is a drawback that the time required for recording increases in proportion to the number of time-divided divisions.

The present invention aims to eliminate the above-mentioned drawbacks of conventional devices by providing a control device in which the same thermal head is not heated in succession without increasing the time required for recording. This is what I am trying to do. Embodiments of the invention will be described below with reference to the drawings.

An example of the overall configuration of the device according to the invention can be shown by the block diagram of FIG. 1, in which case the control circuit 4 becomes the control device of the invention,
In the present invention, the 256 outputs (4000) to (4255) are output from 16 serial input parallel output control shift registers (described in a later section) each having 16 output lines.

FIG. 2 is a timing diagram showing an example of various timings used in the apparatus of the present invention, in which a shows a clock pulse P ₀ and its clock period is t ₀ . b, c, and d in the same figure all show pulses with a sampling period T _s and T _s = 16t ₀ , but b,
The pulses shown in c and d have different generation phases and are represented by P ₁₆ , P ₁₅ , and P ₁₄ . Figure e is P ₁₆ of figure b.
The pulses are shown on a temporal scale, and f in the figure shows the data update period T _N . In the example shown in the figure, T _N =8T _s , and the final sampling period of the data update period T _N is used as the data transfer period. and is indicated by the symbol g(113-128) in the rectangular wave portion of Fig. 2f. g
(113-128) means that it is a gate waveform corresponding to the 113th and subsequent pulses out of 128 P ₀ pulses included in one data update period T _N . Fig. 2g shows Fig. 2f on a temporal scale, h shows the first delay time T _D1 , and Fig. 2i and j show the second delay time T _D2 , respectively. In the example shown in the figure, T _D1 =
4T _N , T _D2 =T _N .

The circuits that use the pulse waveform, gate waveform, etc. shown in FIG. 2 will be explained in order, but to give one numerical example, T _D1 = 1024 μs (microseconds), T _N = 256 μs, T _S = 32 μs, t ₀ =2 μs. Since it is easy to generate each of the waveforms shown in FIG. 2 starting from the P ₀ pulse, a description of the circuit for generating such waveforms will be omitted. Shown in Figure 1
The AD converter 3 outputs digital signals a, . . . h at the time of the _P15 pulse and inputs them to the control circuit 4.

3 and 4 are block diagrams showing an embodiment of the present invention, where the same reference numerals as in FIGS. 1 and 2 indicate the same parts, and 10, 20, and 30 are serial input and serial output shift registers, respectively. The figure shows a set of eight circuits, in which shift register 10 is a 32-bit shift register, and shift registers 20 and 30 are each 8-bit shift registers. The data input to the input terminal of the shift register 10 with a sampling period of T _s = 32 μs is held in the control circuit 4 for a data update period of T _N = 8T _S = 256 μs by a method explained in a later section. The heat generation of the thermal head corresponding to the held data is controlled via the switch element group 5. Retaining data during the data update cycle requires a certain amount of time to heat the thermal head. One thermal head is heated using data from one sampling point, and after this heating is completed, the next one is heated. If the heating of the next thermal head is started based on data from a sampling point, the sampling period must be increased.To avoid this, multiple data from multiple sampling points are retained and all retained Multiple thermal heads corresponding to the data are heated simultaneously.

On the other hand, in order to avoid continuous heating of the same thermal head, when the same digital signal that exists at the output point of any of the shift registers 10, 20, and 30 arrives at the input point of the shift register 10, this signal is The control circuit 4 erases the data so that it is not retained.

By the way, decoding an 8-bit digital signal into 256 types of signals and holding and erasing them requires a large number of circuit elements, so in this invention, as explained in a later section, Signal holding and erasing operations are performed by 16 16-bit shift registers. 11, 21,
31 and 41 are respectively 4-bit presettable counters, D is its input terminal, Q is its output terminal, and L is its load signal input terminal. 12,2
2, 32, and 42 are decoders, respectively, 100 to 115, 200 to 215, and 300 to 31, respectively.
5,400 to 415, and S is an input terminal for a chip enable signal.

500 to 515 (of which 50
The numbers other than 0,501,515 are omitted in the drawing. same as below. ) 600 to 615 are serial input/serial output shift registers, 700 to 715 are serial input/parallel output control shift registers (assuming that they also have a serial output terminal), 50 is an AND gate, 520 to 535, 620~635,720~
735 is an and gate, 540 to 55 respectively
5,640 to 655 are or gates, respectively. The serial input terminals of these shift registers are D,
The serial output terminal is indicated by Q, and the clock input terminal is indicated by CLK.

The counter 11 and the decoder 12 are substitutes for a decoder that inputs an 8-bit digital signal and outputs a logic "1" signal only to one of the 256 output conductors determined by the input digital signal. The circuit configuration is much simpler than that of an 8-bit input decoder, and as will be explained in a later section, an output signal can be obtained in a form suitable for post-processing. The same applies to the combination of counter 21 and decoder 22, the combination of counter 31 and decoder 32, and the combination of counter 41 and decoder 42. Of the digital signals a,...h from the AD converter 3 (generally a signal source), the lower 4 bits a,...d are preset to the counter 11 at the time of the _P16 pulse, and the upper 4 bits e,...h are sent to the decoder. 12 to select one of the 16 conductors 100 to 115. counter 11
Since the P ₀ pulse is continuously input to the terminal Q, a pulse is output from the terminal Q at the timing determined by the preset 4 bits from the time of the P ₁₆ pulse, and the signal of the decoder 12 can be output by the pulse. Make it. That is, 11 and 12 constitute a decoder circuit in which the higher 4 bits of the digital signals a, . . . h determine the signal output line, and the lower 4 bits determine the signal output timing. 2
1, 22, 31, 32, and 41, 42 also constitute similar decoder circuits. Shift register 10 delays the input signal by 32T _s = 4T _N = T _D1 (see Figure 2) and outputs it.
0 and 30, the input signal is further delayed by 8T _S =T _N =T _D2 and output. Decoder circuit 2
1 and 22 decode the output of the shift register 10, and decoder circuits 31 and 32 decode the output of the shift register 2.
0 output and decoder circuits 41 and 42
decodes the output of shift register 30.

Since a circuit that delays an input signal and outputs it is not limited to a shift register, the circuit that provides a delay of T _D1 in the above embodiment is generally referred to as a first-order delay circuit, and the circuit that provides a delay of T _D2 is generally referred to as a first-order delay circuit. This is generally referred to as a second-order delay circuit. In the example shown in FIG. 3, the second-order delay circuit includes two unit delay circuits 20,
30 unit delay circuits are connected in cascade, but it goes without saying that one unit delay circuit or three or more unit delay circuits may be connected in cascade depending on the design. In this specification, decoder circuits 21, 22; 3
1, 32; 41, 42 will be referred to as delayed signal decoder circuits, whereas decoder circuits 11 and 12 will be referred to as signal source signal decoder circuits.

In addition, in this specification, shift registers 600 to
Reference numeral 615 is referred to as a data input shift register, and shift registers 500 to 515 are referred to as blocking shift registers, which are provided corresponding to the signal output conductor of the decoder 12, respectively. We will explain the set of The operations of other groups are similar.

The output of conductor 100 is input to shift register 600 via OR gate 640. However, g11
During the period 3-128, input is blocked by the AND gate 620 and the shift register 600 is cleared. Since the shift register 600 is a 16-bit shift register clocked by the _P0 pulse (the same applies to shift registers 500 and 700), the signal at the input terminal D is delayed by one sampling period T _S and output to the output terminal Q as an OR gate. 640, and is circulated within the shift register 600 and held there.

The operation of the shift register 500 is similar to that of the shift register 600, except that all conductors 200 corresponding to the conductor 100 are connected by the OR gate 540.
The logical sum of 300 and 400 output signals is circulated and held.

That is, as shown in _FIG .
The logical sum of the signals above 0 is stored in the shift register 600, and the logical sum of the signals on the conductor 2 in each sampling period is
The logical sum of the signals on 00, 300, and 400 is stored in shift register 500. During the data transfer period g113-128, the shift register 500,
While blocking the input of 600 and clearing this,
The output of OR gate 640 is input to shift register 700 via AND gate 720 and arranged therein. The shift register 70 is in the OR gate 640.
Since the signal from the serial output terminal Q of 0 is also input, the signal once input to the shift register 700 is circulated and held in the shift register 700 until it is erased by the AND gate 720 by the output of the OR gate 540. be done. Shift register 700 passes through AND gate 50 to g113-1
P ₀ is applied to the clock input terminal CLK for a period of 28 seconds.
Although pulses are input and shifted, the same data is maintained from the end of the data transfer period g113-128 to the start of the next data transfer period, and the thermal head array 6 is controlled via the switch element group 5.

During the data transfer period described above, the OR gate 54
The zero output signal controls the AND gate 720 to block the input to the shift register 700 and removes from the parallel output signals of the shift register 700 any control output signal that would cause the same thermal head to be heated continuously. The output signal of the OR gate 540 is applied to the conductors 200, 300, 400 within the data update period T _N
Since it is the logical sum of the above signals, the existence of the signal here means that (T _D1 ) ~ (T _D1 +
Since it means that the corresponding thermal head was heated before 2T _D2 ) time, AND gate 720 prevents this even if the output signal of OR gate 640 is logic "1" at that time.

As is clear from the above description, according to the present invention, it is possible to reliably prevent heating control signals from being applied successively to the same thermal head without increasing the time required for thermal recording.

In the above explanation, the total number of thermal heads constituting the thermal head array, the total number of control shift registers, the amount of delay in the primary and secondary delay circuits, the data update period, the sampling period, and the sampling period and clock period are explained. Although specific numerical examples have been used for relationships etc., it goes without saying that the present invention is not limited to such numerical examples.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a comprehensive configuration of the present invention, and FIG. 2 is a timing diagram showing an example of various timings used in the device of the present invention.
FIGS. 3 and 4 are block diagrams showing one embodiment of the present invention. 3... AD converter, 4... Control circuit, 5... Switch element group, 6... Thermal head array, 10...
First delay circuit, 20, 30...Second delay circuit, 11, 21, 31, 41...Counter, 12,
22, 32, 42...decoder, 500-515...
Blocking shift register, 600-615...Data input shift register, 700-715...Control shift register.

Claims (1)

[Claims] 1 A signal source that outputs a digital signal at a predetermined sampling period, and when a predetermined plurality of periods of the sampling period is a data update period, the output of the signal source is used as an input signal, and the input signal is a predetermined integral multiple of the data update period. a primary delay circuit that delays and outputs the signal, and a secondary delay circuit configured by cascading one or a predetermined plurality of unit delay circuits that are cascaded to the primary delay circuit and delay the signal by the data update period. input the output signal of the delay circuit, the output signal of the signal source, the output signal of the first delay circuit, and the output signal of each stage of the second delay circuit, and determine the output line of the signal based on the upper bits of the input signal. A decoder circuit for a signal source signal, a decoder circuit for each delayed signal, and each output line of the decoder circuit for a signal source signal, which determines the output timing of the signal within the sampling period based on the lower bits, is provided respectively. A data input shift register and a blocking shift register for delaying the input signal by the sampling period and outputting the same; a data input shift register that is provided corresponding to each of the data input shift registers and having the same number of bits as the data input shift register; and a control shift register equipped with a parallel output terminal, the serial output signal of each of the data input shift registers, the serial signal of the corresponding control shift register, and the signal on the corresponding output line of the signal source signal decoder circuit. Means for setting the logical sum as an input signal of the data input shift register; means for calculating the logical sum of the serial output signals of the respective blocking shift registers and the signals on all the corresponding output lines of the respective delayed signal decoder circuits; means for blocking input to all data input shift registers and all blocking shift registers in the final sampling period of the data update period, and inputting the input signal to each data input shift register. Heating of a thermal head array characterized by comprising means for inputting a signal to each corresponding control shift register, and means for blocking input to the corresponding control shift register based on the input signal of each blocking shift register. Control device.