JPH0132074B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multicolor recording device that records two or more colors on the same recording paper, and particularly relates to a multicolor recording device that records on thermal recording paper that develops multiple colors using a thermal pen. This relates to a recording device.

Heat-sensitive recording paper is conventionally known which develops a red color when heated to a certain temperature R.degree. C., and develops a black color when heated to a temperature higher than R.degree. C., for example, black. On such a recording paper, the first
Conventional two-color recording devices record one analog signal in black and the second analog signal in red, while feeding the recording paper in a fixed direction (assuming the paper feeding direction is the x-axis). ) Move the recording thermal pen by an amount proportional to the amplitude change of the analog signal in the direction perpendicular to this paper feed (temporarily assume the y-axis), and the thermal pen will come into contact with the thermal pen due to the amount of heat applied to it. Thermal recording was performed by increasing the temperature of the recording paper in that area. In order to record the first analog signal and the second analog signal at the same time, a separate thermal pen is used for each signal, and to record the black line, it is necessary to record the red line. More heat was given to the thermal pen for the unit length of the line to be recorded.

In such conventional devices, the driving device for moving the thermal pen is complicated and expensive, and the relative speed between the recording paper and the thermal pen changes, so the amount of force applied to the thermal pen per unit time changes. The temperature of the thermal pen cannot be maintained at a predetermined value unless the amount of heat is changed, and the control device for this purpose becomes complicated.

On the other hand, stationary, thermal, printing, heads, arrays (stationary thermal, printing, heads, arrays)
There is a recording device that uses a printing head array.
In such a recording device, a large number of thermal heads (thermal recording elements) are arranged in a direction perpendicular to the paper feed, that is, in the y-axis direction, and the position in the y-axis direction is adjusted according to changes in the amplitude of the signal to be recorded. A different thermal recording element is selected and the selected thermal recording element is heated to record on the portion of the recording paper that it contacts. Therefore, such a recording device has various advantages such as being able to omit a driving device for the thermal recording element and keeping the relative speed between the thermal recording element and the recording paper constant unless the paper feed speed is changed. However, a device that records multiple types of analog signals in different colors on the same recording paper using stationary, thermal, printing, heads, and arrays has not yet been realized. The object of the present invention is to provide a multicolor recording device capable of recording multiple types of analog signals by color using a stationary, thermal, head, and array.Embodiments of the present invention will be described below with reference to the drawings. do.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the first analog signal is recorded in black, for example, and the second analog signal is recorded in red, for example. When using a stationary, thermal, head, or array, the relative speed between the thermal recording element and the thermal recording paper is kept constant during the recording operation. Or you can record in red.

The structure and operation of the multicolor thermal recording paper, its feeding device, stationary, thermal, head, and array, respectively, are as known in the prior art and are not shown in FIG. 1 in FIG. 1 is a thermal recording element control device that selects an element to be heated from among the stationary, thermal, head, and array, that is, a thermal recording element array, and controls the heating time for the selected element; 2 is a thermal recording element. a control register 3 that holds signals for controlling the control device 1;
4 is an input register for inputting an additional signal to the control register 2, and 4 is a blocking register for erasing part of the signals held in the control register 2.

Further, 51 is an analog-to-digital converter (hereinafter abbreviated as ADC) that inputs an analog signal to be recorded in black and converts it into a digital signal, and 52 is an ADC that inputs an analog signal to be recorded in red and converts it into a digital signal. , 61 is a delay device that inputs the output of the ADC 51 and delays the output by the energization time t _B for black recording, and 62 inputs the output of the ADC 52 and delays the energization time t _R for red recording. The output delay device 71 is a signal source signal decoder device that inputs the output of the ADC 51 and separates and outputs all types of signals determined by this input signal. For example, the output of the ADC 51 is a binary 8
In the case of a bit digital signal, the output of the signal source signal decoder device 71 becomes 2 ⁸ =256 types of binary signals. 72, 81, and 82 are also decoder devices similar to 71, and 72 is referred to as a source signal decoder device, and 81 and 82 are respectively referred to as delayed signal decoder devices. The input register 3 inputs the logical sum of the corresponding output signals of the decoder devices 71 and 72, and the blocking register 4 inputs the logical sum of the corresponding output signals of the decoder devices 81 and 82. 31 is a gate device provided for adding the signal held in the input register 3 to the control register 2, and 21 is a gate device for adding the signal held in the control register 2 to the signal held in the blocking register 4. It is provided for erasing by reading.

Decoder devices 71, 72, 81, 8 of this invention
2 and registers 2, 3, and 4, any decoder device and any register may be used, but
To explain using the numerical example above, there are 256 types of 2
Processing a value signal (therefore, one type of signal can be represented by one bit) with all bits in parallel requires a large number of gate circuits,
On the other hand, if all bits are processed in series, the processing will take a long time. Therefore, as a preferred embodiment of the present invention, an example in which 16 16-bit series circuits are provided in parallel can be considered, and such an embodiment will be described below, but the present invention is not limited to this embodiment. Needless to say, this is not something that can be done.

FIG. 2 is a timing diagram showing an example of the timing used in one embodiment of the present invention. FIG _. 2a shows the clock pulse P ₀ , and FIG. d shows the data update cycle and data transfer period. In the example shown in the figure, the clock period is
t _O , the sampling period t _S is t _S = 16t _O , the data update period t _d is determined as t _d = 8 t _S, and the width of the gate signal g(t) indicating the data transfer period is equal to t _S and the period t _d is The final sampling period is used as the data transfer period. The above-described energization times t _B and t _R have a relationship of, for example, t _B =4t _d and t _R =3t _d .

FIG. 3 shows the ADCs 51, 52, delay devices 61, 62, and decoder devices 71, 72, 81, 8 shown in FIG. 1.
2, the same reference numerals as in FIG. 1 indicate the same parts, 73, 74, 83, and 84 are presettable counters, and
85 and 86 are decoders, and 73 and 75 are the first
The illustrated decoder device 71, 74 and 76 constitute a decoder device 72, 83 and 85 constitute a decoder device 81, and 84 and 86 constitute a decoder device 82, respectively. For each sampling period t _S
The lower 4 bits of the 8 bits of the output signal of the ADC 51 are preset in the counter 73, and the higher 4 bits are output from the output lines _D0 , _D1 ... _D15 by the decoder 75 as determined by the input signal of the decoder 75. Select a line. S is a chip enable signal input terminal of the decoder 75, Q
is a carry signal output terminal of the counter 73. Since the clock pulse P ₀ is input to the counter 73, a signal is output from the terminal Q after a time period corresponding to the preset value has elapsed from the preset time, and the output from the decoder 75 is enabled. That is, 73 and 75 are the top 4 of ADC51.
A decoder device is constructed in which the bits determine the signal output line and the lower 4 bits determine the signal output timing within the sampling period _tS .
The decoder devices constituted by 74 and 76, 83 and 85, and 84 and 86 operate in the same manner. The logical sum of the corresponding output signals of the decoder 75 and the decoder 76 is D ₀ , D ₁ . . . From the output lines of D ₁₅ , the decoder 85
The logical sum of the corresponding output signals of the decoder 86 and
They are output from the output lines I ₀ , I ₁ , . . . I ₁₅ , respectively.

Therefore, input register 3 has output lines D ₀ and D ₁
. . . _A 16-bit shift register is provided for each of the output lines I ₀ , I ₁ , . . . I ₁₅ (16 in total). (16 in total), and the control register 2 has shift registers (16 in total) each having a 16-bit parallel output terminal corresponding to each shift register of the input register 3.

FIG. 4 shows the control register 2, input register 3, blocking register 4, gate device 21, and
This is a connection diagram showing an example of 31, in which output lines D ₀ , D ₁ . . .
Of the 16 sets of circuits corresponding to each of _D15 , only the circuit corresponding to output line _D0 is shown. The same applies to other circuits. In FIG. 4, 200 is a control shift register, 300 is an input shift register, and 40 is a control shift register.
0 is a blocking shift register, 20, 210, 31
0, 320, 410, 420 are gate circuits. In each shift register, D is a serial input terminal, Q is a serial output terminal, CLK is a clock input terminal, and only the control shift register 200 has a parallel output terminal.

The shift registers 300 and 400 are 16-bit shift registers, and a signal is returned from the serial output terminal Q to the serial input terminal D via a gate, and since it is constantly clocked with a clock pulse _P0 , data is transferred every sampling period _tS . One cycle and the output line
Signals from D ₀ and I ₀ are applied to gates 320 and 42, respectively.
It is added logically through 0. However, for each data update period t _d , the period g(t) is the gate 310,
The input is blocked by 410 and the shift register 30
The contents of 0,400 are cleared. The control shift register 200 is clocked via the gate 20 by the clock pulse P ₀ for the duration of the gate signal g(t), during which time the signal on the output line D ₀ held in the shift register 300 is output from its terminal Q. Output signal and control shift register 200
The logical sum of the signals held in itself and output from the terminal Q is inputted through the gate 320, but among these signals, the signal at the same time as the output of the gate 420 is blocked by the gate 210.

The parallel outputs of the control shift register 200 are updated every period of the gate signal g(t) and are sent to the thermal recording element controller 1 for thermal, printing,
Controls the current application time to the recording elements in the head and array.

For example, if the output of the ADC 51 corresponds to the number 12 (in decimal notation) and the output of the ADC 52 corresponds to the number 8 (in decimal notation) at a sampling period of a certain point T _S , then the decoder Pulses are output to the D ₀ output line common to 75 and 76 at output phases corresponding to 8 and 12 of the output phases corresponding to 0 to 15, and these two pulses are input from the gate 320. The next g(t) is held while circulating in the shift register 300.
During the period, the signal is output from the Q terminal of the shift register 300, is input to the control shift register 200 via the gates 320 and 210, and is held. Therefore, from that point in time (temporarily assumed to be T _D ), energization to the 8th and 12th elements in the thermal recording element array is started. After time t _R from the time T _S described above, a signal indicating the numerical value 8 is output to the output of the delay device 62, and an output corresponding to 8 out of the output phases corresponding to 0 to 15 is output to the output line _I0 of the decoder 86. A pulse is output in phase, and this pulse is input from the gate 420 and is held while circulating in the shift register 400, but in the next g(t) period, it is output from the Q terminal of the shift register 400. Control shift register 2 at gate 210 via gate 420
8 that came out from the Q terminal of 00 and passed through gate 320
This pulse is canceled by blocking a pulse with a phase corresponding to . This time point is a time _TR time after T _D , and at this time, the energization of the eighth element in the array of thermal recording elements is terminated. Therefore, the portion of the recording paper under the 8th element that is energized for time _tR develops red. Further, after time t _B from the time T _S described above, a signal indicating the numerical value 12 is output to the output of the delay device 61, and a signal indicating the numerical value 12 is output to the output line _I0 of the decoder 85, which corresponds to 12 of the output phases corresponding to 0 to 15. A pulse is output at the output phase, and this pulse is input from the gate 420 and is held while circulating in the shift register 400, but in the next g(t) period, it is output from the Q terminal of the shift register 400. Then, the pulse having the phase corresponding to 12 coming out from the Q terminal of the control shift register 200 and passing through the gate 320 is blocked and erased at the gate 210 via the gate 420. This time is t _B hours after T _D , and at this time the 12th thermal recording element row
The energization to the th element is terminated. Therefore, the portion of the recording paper under the 12th element, which is energized for time _tB , develops a black color.

As described above, the analog signal input to the ADC 51 is recorded in black, and the analog signal input to the ADC 52 is recorded in red. In actual design, it is often necessary to add a prevention circuit to prevent the thermal recording element from being continuously heated and causing an excessive temperature rise; however, this prevention circuit is not included in the present invention. 1st because there is no direct relationship
Not shown in the diagram. When an overheating prevention circuit is added to the circuit shown in FIG. may be logically added to the corresponding outputs of the decoder devices 81 and 82.

If such a _secondary delay device is provided, the ADC ₅₁ ,
Even if the signal is output from the second delay device 52, continuous energization can be prevented for a predetermined period of time blocked by the signal input to the blocking register 4 from the output of the second delay device.

Although the present invention has been described above for two-color recording of black and red, it is clear that the present invention can be applied to multi-color recording of three or more colors.

As described above, according to the present invention, it is possible to obtain a multicolor recording apparatus that performs multicolor recording using a stationary, thermal, printing, head, and array.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a timing diagram showing an example of timing used in an embodiment of this invention, and FIG. 3 is an example of the decoder device shown in FIG. 1. The block diagram in FIG. 4 is a connection diagram showing an example of the register shown in FIG. DESCRIPTION OF SYMBOLS 1...Thermal recording element control device, 2...Control register, 3...Input register, 4...Block register, 51, 52...ADC, 61, 62...Delay device, 71, 72... Signal source signal decoder device, 81, 82...delay signal decoder device, 7
3, 74, 83, 84...Counter, 75, 7
6, 85, 86...decoder, 200...control shift register, 300...input shift register, 400...blocking shift register.

Claims (1)

[Scope of Claims] 1. A thermal recording paper that develops multiple colors, a thermal recording element array that is arranged on the thermal recording paper and heats the recording paper by elements selected from the array, and A thermal recording element control device that selects an element to be heated from a recording element array and controls the heating time for the selected element, and a thermal recording element control device that selects an element to be heated from a recording element array, and a thermal recording element control device that is provided corresponding to each of the plurality of types of analog signals to be recorded. Each analog-to-digital converter converts an input analog signal into a digital signal having the same number of bits at the same sampling period and outputs the same, and each analog-to-digital converter is provided corresponding to each of the above-mentioned analog-to-digital converters. Each delay device inputs the output of the analog-to-digital converter, delays the input signal by a predetermined delay time, and outputs the delayed signal, and inputs the output signal of each analog-to-digital converter and outputs the delayed input signal by a predetermined delay time. A decoder device for each signal source signal that separates and outputs the signal, and a decoder device for each delayed signal that inputs the output signal of each of the delay devices and separates and outputs all types of signals determined by the input signal. and an input device for inputting the logical sum of the corresponding output signals of all the signal source decoder devices for each sampling period and holding the logical sum of the input signals during a data update period that is a predetermined integral multiple of the sampling period. a register, a blocking register that inputs the logical sum of the corresponding output signals of all the delayed signal decoder devices for each sampling period and holds the logical sum of the input signals during the data updating period; A control register that inputs a data signal updated every last sampling period in the cycle and holds this input signal during the next data update period, and a signal that is held in the control register every last sampling period. The logical sum signal with the signal held in the input register, excluding the signal blocked by the signal held in the blocking register, is input to the control register as the updated data signal. A multicolor recording device comprising: means for erasing the contents of an input register and a blocking register; and means for controlling the thermal recording element control device using a signal held in the control register. 2. Both the source signal decoder device and the delayed signal decoder device are provided with means for determining the output line of the signal based on the upper bits of the input digital signal, and determining the output timing of the signal within the sampling period using the lower bits, and The register includes an input shift register provided corresponding to each output line of the signal source decoder device,
The blocking register includes a blocking shift register provided corresponding to each output line of the delayed signal decoder device, and each of the input shift registers and each blocking shift register delay the input signal by a sampling period. The control register is provided corresponding to each of the input shift registers and has a parallel output terminal. 2. The multicolor recording apparatus according to claim 1, further comprising a control shift register.