JPS6142864B2 - - Google Patents
Info
- Publication number
- JPS6142864B2 JPS6142864B2 JP54073182A JP7318279A JPS6142864B2 JP S6142864 B2 JPS6142864 B2 JP S6142864B2 JP 54073182 A JP54073182 A JP 54073182A JP 7318279 A JP7318279 A JP 7318279A JP S6142864 B2 JPS6142864 B2 JP S6142864B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- chip carrier
- semiconductor element
- hole
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W40/73—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control for cooling by change of state
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の構造に関し、特に半導体
素子の放熱を効果的に行うための構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, and particularly to a structure for effectively dissipating heat from a semiconductor element.
一般に半導体素子に発生する熱を放熱するため
には液冷式と空冷式とがある。 In general, there are liquid-cooling types and air-cooling types for dissipating heat generated in semiconductor elements.
液冷式では半導体素子を収容したチツプキヤリ
アをセラミツク等から成る多層配線板の一表面に
取付け、この配線板の他表面にはコールドプレー
トと呼ばれる冷却器を取付け、その中に水等の冷
媒を流すことによつて半導体素子に生じた熱を放
熱させる。 In the liquid cooling type, a chip carrier containing semiconductor elements is attached to one surface of a multilayer wiring board made of ceramic or the like, and a cooler called a cold plate is attached to the other surface of this wiring board, and a coolant such as water is flowed through it. In this way, the heat generated in the semiconductor element is radiated.
一方、空冷式では液冷式と同様に配線板のチツ
プキヤリアを取付けた側とは反対側の表面に放熱
フインを設けて半導体素子に生じた熱を放熱させ
る。 On the other hand, in the air-cooled type, as in the liquid-cooled type, heat radiation fins are provided on the surface of the wiring board opposite to the side on which the chip carrier is attached to radiate heat generated in the semiconductor element.
従来、このような水冷式および空冷式のいずれ
においても、半導体素子において発生した熱は半
導体素子を収容するチツプキヤリアおよび配線板
を介して裏面の放熱器に達しており、このような
構造では配線板の熱抵抗が大きいために放熱が効
果的に行われないという欠点があつた。 Conventionally, in both the water-cooled type and the air-cooled type, the heat generated in the semiconductor element reaches the heat sink on the back side via the chip carrier that houses the semiconductor element and the wiring board. The disadvantage is that heat dissipation cannot be carried out effectively because of the high thermal resistance.
本発明は、従来のこのような欠点を解決し、半
導体素子において発生した熱をより効果的に放熱
することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional drawbacks and more effectively dissipate heat generated in a semiconductor device.
このような本発明の特徴は、
一表面から他表面へ貫通する穴部を有すると共
に内部に配線を有する配線板と、
半導体素子を搭載し該半導体素子に導通する接
続部を表面部に有するチツプキヤリアと、
放熱器内に所定の空間を有する放熱器とから成
り、該配線板の一表面と該チツプキヤリアの前記
表面部とを該配線板の穴部を覆うようにソルダ材
により封着すると共に該表面部の接続部を配線板
に電気的に接続し、該配像板の他表面において該
穴部を覆うように該放熱器を装着し、
該放熱器と該配線板と該チツプキヤリアとによ
り冷媒を封止したことにある。 The features of the present invention include: a wiring board having a hole penetrating from one surface to the other surface and having wiring therein; and a chip carrier having a semiconductor element mounted thereon and having a connection part conductive to the semiconductor element on the surface part. and a heat radiator having a predetermined space within the heat radiator, one surface of the wiring board and the surface portion of the chip carrier are sealed with a solder material so as to cover the hole of the wiring board, and the A connection part on the surface part is electrically connected to the wiring board, and the radiator is mounted on the other surface of the distribution board so as to cover the hole part, and the refrigerant is dissipated by the radiator, the wiring board, and the chip carrier. The reason is that it has been sealed.
以下図面を参照して本発明を説明する。 The present invention will be explained below with reference to the drawings.
第１図は本発明による半導体装置の一実施例の
断面図である。 FIG. 1 is a sectional view of an embodiment of a semiconductor device according to the present invention.
半導体素子１はモリブデンMoなどの熱伝導性
の良い金属からなるメタル・ダイステージ４が接
着されたチツプキヤリア２内に収容され、蓋６に
より気密封止される。 The semiconductor element 1 is housed in a chip carrier 2 to which a metal die stage 4 made of a metal with good thermal conductivity such as molybdenum Mo is bonded, and hermetically sealed with a lid 6.
チツプキヤリア２は鉛Pbと錫Snから成るソル
ダ材７，８により穴部９′を有するセラミツクの
多層配線板９に穴部９′を覆うようにして取付け
られている。 The chip carrier 2 is attached to a ceramic multilayer wiring board 9 having a hole 9' using solder materials 7 and 8 made of lead Pb and tin Sn so as to cover the hole 9'.
またチツプキヤリア２には導電体５が設けられ
チツプキヤリア内部において半導体素子１とはワ
イヤ３により接続され、チツプキヤリア外部にお
いては、ソルダ材８を介して配線板９内部に形成
された図示しない配線と接続されている。 Further, the chip carrier 2 is provided with a conductor 5, which is connected to the semiconductor element 1 by a wire 3 inside the chip carrier, and connected to a wiring (not shown) formed inside the wiring board 9 via a solder material 8 outside the chip carrier. ing.
配線板９のチツプキヤリア２が取付けられた表
面と反対側の表面には中空であり、かつ放熱フイ
ン１１を有する放熱器１０がチツプキヤリアと同
様に穴部９′を覆うように取付けられており、こ
の放熱器中には所定の空間１４を有してフレオン
CF4などの低沸点の冷媒１２が配線板９、チツプ
キヤリア２（メタルダイステージ４、ソルダ材７
を含む）と共に封止されている。 On the surface of the wiring board 9 opposite to the surface on which the chip carrier 2 is attached, a hollow heat radiator 10 having heat dissipating fins 11 is installed so as to cover the hole 9' like the chip carrier. A predetermined space 14 is provided in the heat radiator, and the Freon
A low boiling point refrigerant 12 such as CF 4 is applied to the wiring board 9, chip carrier 2 (metal die stage 4, solder material 7).
(including).
このような構造において、半導体素子を動作さ
せ熱が発生すると、この熱はメタルダイステージ
４を介して冷媒１２に伝達する。 In such a structure, when the semiconductor element is operated and heat is generated, this heat is transferred to the coolant 12 via the metal die stage 4.
この際、冷媒として沸点が40℃〜50℃の低温で
あるフレオンは沸謄して気化する。 At this time, Freon, which has a boiling point at a low temperature of 40°C to 50°C, is boiled and vaporized as a refrigerant.
従つて、半導体素子に発生した熱は気化熱とし
てうばわれると共に気化して空間１４中に存在す
るフレオンガスは放熱フイン１１よりその熱がう
ばわれ、温度が下がつて再び液化する。 Therefore, the heat generated in the semiconductor element is dissipated as heat of vaporization, and the freon gas present in the space 14 is dissipated from the heat dissipation fin 11, and its temperature is lowered to liquefy again.
冷媒としてのフレオンは半導体素子から発生す
る熱によりこのような気化と液化の過程をくり返
しこの間に発生した熱は消費、放熱され、半導体
素子の温度が一定値以上は上昇しないようにする
ことができる。 Freon, which is used as a refrigerant, repeats the process of vaporization and liquefaction using the heat generated by the semiconductor element, and the heat generated during this process is consumed and dissipated, making it possible to prevent the temperature of the semiconductor element from rising above a certain value. .
このように従来とは異なり、熱抵抗の大きい配
線板に穴部を設けて冷媒がチツプキヤリア（主に
メタルダイステージ）に直接接触するようにした
ので放熱を効果的に行うことができる。 In this way, unlike conventional designs, holes are provided in the wiring board with high thermal resistance so that the refrigerant comes into direct contact with the chip carrier (mainly the metal die stage), making it possible to effectively dissipate heat.
第２図は本発明の他の実施例を示す断面図で、
第２図と同じ番号は同じものを示す。 FIG. 2 is a sectional view showing another embodiment of the present invention,
The same numbers as in FIG. 2 indicate the same things.
本実施例が第１図に示した実施例と異なる点は
半導体素子を上向きにし、第１図のようにメタル
ダイステージ４を介すことなく半導体素子が直接
冷媒と接触する構造とした点にある。 This embodiment differs from the embodiment shown in FIG. 1 in that the semiconductor element is oriented upward, and the semiconductor element is in direct contact with the coolant without going through the metal die stage 4 as shown in FIG. be.
この様な構造とすることにより、簡単な構造の
チツプキヤリアを用いて放熱効果のよい半導体装
置が得られる。 With such a structure, a semiconductor device with good heat dissipation effect can be obtained using a chip carrier with a simple structure.
尚、冷媒としてのフレオンは不活性であり、こ
のように半導体素子と直接接触させても何ら支障
はない。 Note that Freon as a refrigerant is inert, and there is no problem even if it is brought into direct contact with the semiconductor element in this way.
また、配線板と放熱器の接着は鉛Pb、錫Sn、
インジウムInの合金や、エポキシ系樹脂を用いて
行なうことができる。 In addition, the adhesive between the wiring board and the heatsink is made of lead Pb, tin Sn,
This can be done using an indium In alloy or an epoxy resin.
さらに、第１図と第２図の実施例において冷媒
の注入は放熱器１０の上部に設けた注入口１３よ
り行ない、注入後は注入口をかしめて封止する。 Furthermore, in the embodiments shown in FIGS. 1 and 2, the refrigerant is injected through an inlet 13 provided at the top of the radiator 10, and after injection, the inlet is caulked and sealed.
以上説明した通り本発明によれば、簡単な構造
により放熱効果のよい半導体装置が実現される。
また、このような構造の半導体装置では冷媒がう
ばう気化熱はかなり大きいため、例えば第１図の
実施例のメタルダイステージの面積を大きくして
放熱面積を大きくするまでもなく充分放熱効果が
あるので、配線板に設けた穴部やこれを覆う放熱
器の寸法を小さくすることができ、半導体装置の
小型化も図られる。 As explained above, according to the present invention, a semiconductor device with a simple structure and good heat dissipation effect can be realized.
In addition, in a semiconductor device having such a structure, the heat of vaporization of the coolant is quite large, so for example, there is no need to increase the area of the metal die stage in the embodiment shown in Fig. 1 to increase the heat dissipation area, and the heat dissipation effect is sufficient. Therefore, the dimensions of the hole provided in the wiring board and the heat sink covering the hole can be reduced, and the size of the semiconductor device can also be reduced.
第１図は本発明の一実施例を示す断面図、第２
図は他の実施例を示す断面図である。
図において、１は半導体素子、２はチツプキヤ
リア、９は配線板、９′は穴部、１０は放熱器、
１１は放熱フイン、１２は冷媒、１４は空間を示
す。
FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
The figure is a sectional view showing another embodiment. In the figure, 1 is a semiconductor element, 2 is a chip carrier, 9 is a wiring board, 9' is a hole, 10 is a heat sink,
11 is a heat radiation fin, 12 is a refrigerant, and 14 is a space.
Claims (1)
共に内部に配線を有する配線板と、 半導体素子を搭載し該半導体素子に導通する接
続部を表面部に有するチツプキヤリアと、 加熱器内に所定の空間を有する放熱器とから成
り、 該配線板の一表面と該チツプキヤリアの前記表
面部とを該配線板の穴部を覆うようにソルダ材に
より封着すると共に該表面部の接続部を配線板に
電気的に接続し、 該配線板の他表面において該穴部を覆うように
該放熱器を装着し、 該放熱器と該配線板と該チツプキヤリアとによ
り冷媒を封止したことを特徴とする半導体装置。 ２ 一表面から他表面へ貫通する穴部を有すると
共に内部に配線を有する配線板と、 半導体素子を搭載し該半導体素子に導通する接
続部を表面部に有するチツプキヤリアと、 放熱器内に所定の空間を有する放熱器とから成
り、 該配線板の一表面と該チツプキヤリアの前記表
面部とを該配線板の穴部を覆うようにソルダ材に
より封着すると共に該表面部の接続部を配線板に
電気的に接続し、 該配線板の他表面において該穴部を覆うように
該放熱器を装着し、 該放熱器と該配線板と該チツプキヤリアの半導
体素子搭載面の裏面とにより形成される空間に冷
媒を封止したことを特徴とする半導体装置。[Scope of Claims] 1. A wiring board having a hole penetrating from one surface to the other surface and having wiring therein; A chip carrier having a semiconductor element mounted thereon and having a connection part conductive to the semiconductor element on the surface part; and a radiator having a predetermined space within the heater, one surface of the wiring board and the surface portion of the chip carrier are sealed with a solder material so as to cover the hole in the wiring board, and the surface portion electrically connect the connecting portion of the wiring board to the wiring board, install the heat radiator on the other surface of the wiring board so as to cover the hole, and seal the refrigerant with the heat radiator, the wiring board, and the chip carrier. A semiconductor device characterized by: 2. A wiring board having a hole penetrating from one surface to the other surface and having wiring therein; a chip carrier having a semiconductor element mounted thereon and having a connection part conductive to the semiconductor element on its surface; a heat sink having a space, one surface of the wiring board and the surface portion of the chip carrier are sealed with a solder material so as to cover the hole in the wiring board, and a connecting portion of the surface portion is connected to the wiring board. electrically connected to the wiring board, the heat radiator is mounted on the other surface of the wiring board so as to cover the hole, and the heat radiator is formed by the heat radiator, the wiring board, and the back surface of the semiconductor element mounting surface of the chip carrier. A semiconductor device characterized by a space sealed with a refrigerant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7318279A JPS55165658A (en) | 1979-06-11 | 1979-06-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7318279A JPS55165658A (en) | 1979-06-11 | 1979-06-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55165658A JPS55165658A (en) | 1980-12-24 |
| JPS6142864B2 true JPS6142864B2 (en) | 1986-09-24 |
Family
ID=13510733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7318279A Granted JPS55165658A (en) | 1979-06-11 | 1979-06-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55165658A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2604827B1 (en) * | 1986-10-06 | 1989-12-29 | Alsthom | VAPORIZED COOLING DEVICE FOR POWER SEMICONDUCTORS |
| GB2380057A (en) * | 2001-09-19 | 2003-03-26 | Thermosonic Technology Inc | Heat dissipation structure with cavity for improved heat transfer |
| KR100461721B1 (en) * | 2002-05-27 | 2004-12-14 | 삼성전기주식회사 | Ceramic package for transfering heat through lid |
| US20060090881A1 (en) * | 2004-10-29 | 2006-05-04 | 3M Innovative Properties Company | Immersion cooling apparatus |
| US7755186B2 (en) * | 2007-12-31 | 2010-07-13 | Intel Corporation | Cooling solutions for die-down integrated circuit packages |
| JP5880318B2 (en) * | 2012-07-04 | 2016-03-09 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53135579A (en) * | 1977-05-02 | 1978-11-27 | Hitachi Ltd | Liquid sealing semiconductor device |
-
1979
- 1979-06-11 JP JP7318279A patent/JPS55165658A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55165658A (en) | 1980-12-24 |
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