JPS6145440B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for driving a space-division communication path using a semiconductor switch which maintains its conductive state by a flowing current as a point element. Among the space-division type communication paths, which are one type of communication paths in exchanges for telephones and the like, there are some that use semiconductor switches such as PNPN transistors, photoPNPN transistors, and triacs as point elements. Since these semiconductor switches have the characteristic of self-maintenance by the current flowing through them, if they are used as point elements, it is possible to construct a communication path of the communication current holding type that can maintain the communication route with the communication current.
This communication current holding type communication path also has the advantage of being able to construct an economical communication path since it is not necessary to add a special circuit for point maintenance. However, in this type of communication line that maintains communication current, when the subscriber line is disconnected, the communication line switch is opened because the communication current disappears. Such conditions occur when signals are sent and received between the subscriber's telephone and the exchange, such as when a dial pulse signal is sent from the telephone, or when a ringing signal or a billing signal is sent from the trunk; This occurs when an unexpected momentary interruption occurs in the subscriber line due to noise, etc. As a countermeasure against disconnection of communication current in a telephone current holding type communication path, as shown in Fig. 1, a cyclic access type link holding memory is provided in the switch control circuit, and the contents of the link holding memory are read out periodically. A periodic drive method (see Japanese Patent Application No. 13366/1983) is used to drive the communication path. In Figure 1, LHM is a cyclic access type link holding memory, MAT is a PNPN transistor,
It is a switch matrix composed of point elements with current self-holding functions such as photo-PNPN transistors and triacs. IN0 to IN (n-1) are the input terminals of the switch matrix MAT, and OUT0 to OUT
(m-1) is the output terminal of switch matrix MAT, X0~X(n-1) and Y0~Y(m-1)
is a terminal that specifies the point to be driven in MAT. Further, CTR is a counting circuit that specifies the read address of the link holding memory LHM and, at the same time, specifies, for example, the output terminal number of the switch matrix MAT. The input terminal number is stored in the link holding memory LHM, and DEC0 is the link holding memory.
A decoder that expands connection information in LHM, DEC/
is a decoder that expands the output information of CTR.
The operation of this will be explained next. When a call route connection request is sent from a control device (not shown), a write circuit (not shown) of the link holding memory LHM writes an input terminal number to an address corresponding to the output terminal with the connection request. On the other hand, all the information in the link holding memory LHM is read out once in one cycle under the control of the counting circuit CTR. For example, at the time when the connection information of output terminal 1 is being read out, the output of the counting circuit CTR is 1, the call route to be driven can be specified by the connection information of the link holding memory LHM and the information of the output of the counting circuit CTR. Since the switch control circuit has such a configuration, even if the switch is turned off due to a disconnection of the communication current, the communication path is driven again in the next drive cycle, the communication current flows, and the switch maintains its current self. . The periodic drive method utilizes the current self-holding function of the switch to minimize the metal parts of the communication path holding circuit, and also shortens the driving time for one communication path, thereby reducing driving power. This is an extremely effective method for downsizing and making it more economical.
However, the periodic driving method has the following problems, and the conventional technology imposes a limit on the scale of the communication path to which it can be applied. That is, when a periodic drive method is applied to a signal in which communication current is interrupted among signals transmitted and received between a telephone set and an exchange, the waveform is distorted by the maximum drive period. Therefore, it is necessary to design the drive cycle to be sufficiently short so that waveform distortion does not affect the exchange operation. In existing exchanges, the signal with the shortest intermittent cycle of current among the signals that cause intermittent communication current is the Howler signal, and the intermittent cycle of current is 400.
It is Hz. Therefore, if the waveform distortion of the Howler signal is allowed to be 10%, the drive cycle will be 4KHz. On the other hand, semiconductor switches such as PNPN transistors, photo-PNPN transistors, and triacs have a relationship as shown in FIG. 2 between the driving pulse width and the minimum driveable gate current. This second figure is an existing
This shows an example of the drive characteristics of a PNPN transistor, where the vertical axis represents the switch driving pulse T _w in nanoseconds, and the horizontal axis represents the minimum driveable gate current I _g
is expressed in mA. In Fig. 2, the switch can be driven in the area above curve a, but
It cannot be driven in the lower area. On the other hand, in FIG. 1, decoders DEC0,
DEC1, link holding memory LHM, counting circuit CTR
each consists of a logic circuit, so if the switch can be driven by a logic signal, the decoder
The switch can be driven by connecting the outputs of DEC0, DEC1 and the counting circuit CTR as they are to the selection drive line of the switch, which is extremely economical as there is no need for a level conversion circuit such as a switch driver required for an electromagnetic switch. For example, the maximum supply current of a TTL logic element is about 15 mA, so if the gate current can be designed to be 15 mA or less, it will be possible to drive the switch with a logic signal. However, from Fig. 2, when the gate current I _g is 15 mA, the driving pulse width T _w is
Since it is about 250nsec, the number of output lines of the matrix that can be driven by one switch control circuit is 250μsec/
It is limited to 0.25μsec or about 1.000 terminals.
Here, 250μsec is 1 of the drive cycle of 4KHz mentioned above.
corresponds to a cycle. On the other hand, existing exchanges such as D10
Since the maximum number of outgoing terminals in a type electronic switchboard is 12,000 terminals, applying the periodic drive method had the disadvantage of greatly restricting the scale of the switchboard and limiting the types of switchboards to which it could be applied. It is an object of the present invention to eliminate the drawbacks of the periodic drive method described above and to make it possible to apply it to large-scale communication paths by appropriately dividing control units. Examples will be described in detail below. FIG. 3 shows an embodiment of the present invention.
LLN1 to LLN3 each represent one switch matrix block. LHM1 is a switch matrix LLN1, TLN1, LHN2 is a switch matrix LLN2, TLN2, LHM3 is a switch matrix
CTR is a cyclic access type link holding memory that drives each of LLN3 and TLN3, and is a counting circuit. OUT10~OUT32 are output terminals of switch matrix LLN1~LLN3, IN10
~IN32 is switch matrix TLN1~TLN
No. 3 input terminals, X10-X32, Y10-Y32, represent terminals for specifying the crosspoints to be driven in each switch matrix. The counting circuit CTR specifies the read address of the link holding memories LHM1 to LHM3, and also specifies the read address of the link holding memories LHM1 to LHM3 and also specifies the read address of the link holding memories LHM1 to LHM3 and
LLN3 output terminal number and switch matrix
Specify the input terminal numbers of TLN1 to TLN3. Third
In the configuration shown in the figure, each output value of the counting circuit CTR and the control terminals X10 to X3 driven thereby
0 and Y10 to Y32 are associated as shown in Table 1.

[Table] At this time, the link drive timing is as shown in Figure 4, and the call route driven by the drive timing is only one for each switch matrix.
(specified by the output of CTR and the output of LHM), and the switch matrix
Switches connected to a specific link connecting LLN1 to LLN3 and TLN1 to TLN3 are always driven at the same timing. The former condition is an essential condition in order to close only one junction in the switch matrix in the XY selection method, and the latter condition requires that all switches on the drive route with connection requests be driven at the same time. This is a necessary condition because without it, the communication current loop would not be possible. These two conditions are necessary and sufficient conditions for the periodic drive method. FIG. 5 shows another embodiment of the present invention, in which the same reference numerals as in FIG. 3 represent the same elements. Although the control terminals X10 to Y32 in FIG. 3 are omitted, the wiring method is the same as that in FIG. 3. The difference between FIG. 3 and FIG. 5 is that in FIG. 3, a plurality of link holding memories LHM are provided corresponding to the switch matrices, but in FIG.
The point is that LHM has been unified into one. At this time, the link holding memory LHM is stored at address 0.
OUT10, IN10, OUT21, IN21, OUT
Information on the control terminals of the call routes of switch matrices LLN1 to LLN3 and TLN1 to TLN3 connected to each terminal of IN32 and IN32 is written as data. This method focuses on the fact that the control terminals are driven at the same time as shown in FIG. 4, and makes the link holding memory LHM more compact and economical. As explained above, according to the present invention, the channel control operation can be performed without any problem when a multi-stage channel is configured using a plurality of switch matrices, so there are no restrictions on the scale of the channel in the periodic driving method. can be removed. Further, by applying the present invention, the number of hardware such as a link holding memory and a counting circuit is not particularly increased, and an economical drive circuit can be constructed.

[Brief explanation of the drawing]

Figure 1 is a block diagram for explaining the principle of the periodic drive system, Figure 2 is a diagram for explaining the drive characteristics of an existing PNPN transistor, Figures 3 and 5 are block diagrams for the embodiment of the present invention, and Figure 4. is a time chart of an example of drive timing according to the present invention. MAT, LLN1, LLN2, LLN3, TLN1,
TLN2, TLN3, LLN _o , TLN _n are switch matrices, IN0 to IN (n-1), IN10 to IN32 are matrix input terminals, OUT0 to OUT (m-
1), OUT10 to OUT32 are output terminals of the matrix, X and Y are control terminals of the switch matrix,
LHM, LHM1, LHM2, and LHM3 are cyclic access type link holding memories, DEC is a decoder, and CTR is a counting circuit.

Claims (1)

[Scope of Claims] 1. In a communication path drive system for a space-divided communication path of a communication current holding type configured to maintain the communication path by periodically driving a communication path switch, (a) A plurality of communication path stages each using a plurality of switch matrices each having an X control terminal for driving an input terminal and a Y control terminal for driving an output terminal are provided,
A multi-stage communication path configured by connecting the output terminal of each switch matrix in the previous stage and the input terminal of each switch matrix in the subsequent stage with a communication link, and (b) a counter that cyclically outputs the count value. (c) a first circuit that decomposes the output of the counting circuit into output values;
(d) a cyclically accessed memory cyclically accessed by the counting circuit; and (e) a plurality of second decoders that decompose each output of the cyclically accessed memory into output values. (f) The output of the first decoder is connected to the Y control terminal of each switch matrix in the preceding stage and each switch matrix in the subsequent stage while the count value of the counting circuit goes through one cycle.
The X control terminal of each matrix is driven once, and so that two or more control terminals in the same matrix are not driven at the same time, it corresponds to the Y control terminal of each previous stage switch matrix and the X control terminal of each subsequent stage switch matrix. (g) Each time a call path connection request is made, the cyclic access memory stores information corresponding to the call route determined in response to the connection request as information corresponding to the X control terminal of the switch matrix in the previous stage. (h) the outputs of the plurality of second decoders are held at the address position corresponding to the output of the counting circuit; X control terminal or Y of the subsequent switch matrix
1. A communication path driving system, which is connected to a control terminal, and (i) selects and drives a connected communication route based on the output of the first decoder and the output of the second decoder.