JPS6347186B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a talkie connection service in a digital exchange, and particularly to a digital polyphase talkie device having a polyphase output function.

(2) Background of the technology In general, switched connection services are equipped with trunks for sending messages and use voice announcement services or talkie services.

(3) Problems with the conventional technology In this type of conventional technology, the talkie information storage format uses analog information, and the device itself is mechanical, which has drawbacks such as deterioration of sound quality and mechanical failure.
Furthermore, when sending out talkies to a plurality of subscribers, etc., there were economical problems, such as the need to provide talkie devices for simultaneous connections.

(4) Purpose of the invention In order to solve the above-mentioned problems, the purpose of the present invention is to store message information (voice information) as digital information, form a cyclic loop within the storage device, and store the digital information. The purpose of the present invention is to provide a talkie device that circulates around and obtains multiphase output.

(5) Structure of the Invention In order to achieve the above object, the present invention connects a plurality of memories that store a series of analog audio as digital information in a loop form to form a large-capacity shift register. an address counter for specifying read and write operation timing and addresses; and an output terminal for outputting the digital information from between the respective memories; In addition to moving data from
The present invention is characterized in that talk information having a phase shift is output to each of the output terminals.

(6) Examples of the invention The present invention will be explained in detail below using examples. FIG. 1 shows an example of the configuration of an exchange system using the talkie device of the present invention. In the figure, TDNW is a digital network, SPC is a network control device, CPU is a central processing unit, MEM is a storage device,
MPX and DMPX are multiplexers and day multiplexers, SUB is a subscriber telephone, TRK is a trunk, and TK is a talkie device of the present invention. Although the general switching operation of a digital switch is well known and a detailed explanation will be omitted, the talkie device of the present invention has n output terminals and can simultaneously supply n channels to subscriber lines and trunk lines.

FIG. 2 shows a configuration diagram of an embodiment of the talkie device of the present invention. In the figure, RAM1 to N are random access memories, in this example 64K bit memories, and N RAMs are used to send out a series of announcement information (for example, "On the XX line right now...
...Please try again later.'').The IDC consists of a code conversion circuit that converts input data into digital data, an input start time storage circuit,
AC is an address counter and read/write timing control circuit, LSW1 to N are loop switches, ISW is an input switch, INV is a monitor digital/analog decoder, a is an analog information input terminal, b is a monitor terminal, c is 64kHz for example The clock terminals _l1 to _l4 are coordinates indicating the range of the cyclic loop. In addition, switch LSW1~N,
The ISW is composed of a semiconductor gate circuit and can be selected by gate control from the CPU.

Here, 30 pieces of 64K bit RAM (N=30)
If prepared, output terminal from each RAM1 to N
By taking out OUT1 to N, the number of phases becomes 30. In this configuration, first, in order to input (write) the talkie information, the input switch ISW is closed, and the loop switches LSW0 to LSWN are opened. Considering that the analog information of the talkie is currently 30 seconds (or 29 seconds or more and less than 30 seconds) and digitized information is written to each RAM in units of 1 second, input analog voice information from analog input terminal a and write the code. The conversion circuit IDC converts it into digital information (PCM code) and inputs it to RAM1.
It also stores the input start time. Correspondingly, the address counter AC starts counting in response to a 64K bit/S clock pulse c, and performs write/read operation timing control and address designation of RAM1-N. That is, the address counter AC is
It performs a cycle count of 64000/second. Between each RAM1-N, 64K bits of information are sequentially moved from the 0th bit to the 63999th bit simultaneously in read and write cycles. When all data (64K bits x N) has been written, that is, 30 seconds in this example, the input switch ISW is opened and the loop switch LSW30 is closed to close the loop (l ₁ in Figure 2).
→l ₂ →l ₃ →l ₄ - forms a large-capacity shift register (loop shown by l ₁ ). Then the address counter
Each bit according to AC addressing
Data movement (shift operation from the previous RAM to the subsequent RAM) is performed at the same address in RAM 1 to RAM N at intervals of 15.625 μs, and the output terminal OUT
Information read from each RAM 1 to N is sequentially branched and output. At this time, the talkie information is sent to the output terminals 1 to N in a form that is shifted at one second intervals.

FIG. 3 shows the writing/reading timing relationship of talkie information. This diagram shows the RAM in Figure 2, RAMm,
m+1 and m+2 are shown as examples, and bit addresses 0 to M-1 (63999) are common to each RAM.
It is specified by the address counter AC every 15.625 μs (1/64k) and is incremented every 15.625 μs. For the same address, read R is performed first within 1 bit period (15.625 μs), and the read bit pulse RP Write inside. In other words, the read/write address is specified by the address counter AC with a cycle of 15.625 μs (1/64 Kbit), and the cycle T is set to 1.
If it is a second, it will be 64K bits, and 64K RAM will be N
If two units are provided, messages for N seconds can be stored and a phase of every second can be taken out from each output terminal.
Although the example of closing the loop switch LSW30 in Fig. 2 was explained, if you arbitrarily select LSWi, the memory can be set to satisfy the message length.
RAM can be used.

Next, a phase selection method for locating an arbitrary time when connecting to a tone device in response to a request from a line as shown in FIG. 1 will be explained.

If the cycle loop time length is T, the interphase time is t (phase difference between RAMs), the request time is t1, and the initial setting time of the talkie (the time when the beginning of the message is at the input point of RAM1) is t0, the request time is
The output terminal number No. of the talkie device at t1 is obtained by No=G[R[ _t1 - _t0 /T]/t]+1.

However, R [r/m] is the remainder of division r/m, G
[A] indicates the rounded down number of A.

(7) Effects of the Invention As explained above, according to the present invention, talk information can be stored in digital format using a loop-type large-capacity shift register using memory, and multiphase output can be obtained. Quality audio can be guaranteed and cue control becomes easy. Furthermore, since the talkie device can be configured with memory and gate circuits, it can also be implemented as an LSI.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an exchange system as an example equipped with the talkie device of the present invention, FIG. 2 is a configuration diagram showing an embodiment of the talkie device of the present invention, and FIG. 3 is a timing chart for writing and reading talkie information. be. RAM1~N: Memory, IDC: Code conversion circuit,
PSDG: Bilot counter, LSW1~N: Loop switch, ISW: Input switch, OUT1~
N: output terminal, INV is a monitor digital/analog decoder, a is an analog information input terminal, b is a monitor terminal, and c is a clock terminal.

Claims (1)

[Claims] 1. A plurality of memories RAM1 to RAMN that store a series of analog audio as digital information are connected in a loop to form a large-capacity shift register, and the timing and timing of read and write operations for each memory are determined. An address counter (AC) that specifies an address and output terminals OUT1 to output the digital information from each of the memories.
OUTN, and is configured to move data from the previous memory to the subsequent memory at the same address in each of the memories according to the address designation of the address counter, and to output phase-shifted talk information to each of the output terminals. A digital multiphase talkie device with special features.