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JPS6146972B2 - - Google Patents
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JPS6146972B2 - - Google Patents

Info

Publication number
JPS6146972B2
JPS6146972B2 JP53121828A JP12182878A JPS6146972B2 JP S6146972 B2 JPS6146972 B2 JP S6146972B2 JP 53121828 A JP53121828 A JP 53121828A JP 12182878 A JP12182878 A JP 12182878A JP S6146972 B2 JPS6146972 B2 JP S6146972B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
conductivity type
element isolation
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53121828A
Other languages
Japanese (ja)
Other versions
JPS5548958A (en
Inventor
Tomonobu Yoshitake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP12182878A priority Critical patent/JPS5548958A/en
Publication of JPS5548958A publication Critical patent/JPS5548958A/en
Publication of JPS6146972B2 publication Critical patent/JPS6146972B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、一つのペレツトに2個以上のPNダ
イオードが形成されたプレーナ型半導体装置に関
し、特に各ダイオード間の不要結合を阻止するた
めの分離層に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a planar semiconductor device in which two or more PN diodes are formed in one pellet, and particularly to a separation layer for preventing unnecessary coupling between the diodes.

一般に、一つのペレツト(基板)にプレーナ構
造により複数個のダイオードが形成されてなる半
導体装置は、第1図に示すような構造をもつ。す
なわち、一つのN型半導体基板1に、二酸化シリ
コン膜3にあけられた複数個の拡散窓から拡散さ
れたP型不純物により形成された複数個のP層2
a,2b,………をアノード層とし、N型基板1
を共通のカソード層とし、各アノード層2a,2
b,………にはそれぞれ電極金属4a,4bが被
着され、かつ、接様端子A1,A2が、そして、共
通カソード端子としてKが引出されている。さら
に、場合により、各P層間に、N型不純物を高濃
度に含むN+のチヤンネルストツパ5が設けられ
ている。
Generally, a semiconductor device in which a plurality of diodes are formed in a planar structure on one pellet (substrate) has a structure as shown in FIG. That is, in one N-type semiconductor substrate 1, a plurality of P layers 2 are formed by P-type impurities diffused from a plurality of diffusion windows formed in a silicon dioxide film 3.
a, 2b, ...... are anode layers, and an N-type substrate 1
are used as a common cathode layer, and each anode layer 2a, 2
Electrode metals 4a and 4b are respectively applied to b, . Further, depending on the case, an N + channel stopper 5 containing a high concentration of N type impurity is provided between each P layer.

第2図は、第1図の半導体装置のダイオード素
子2個の使用例回路図であり、第2図において、
入力トランス21を通して端子A1,A2間に加え
られる入力交流は、素子2aを通してコンデンサ
22を充電し、コンデンサ22の端子間電圧がK
端子とA2端子間に並列に接続された2端子PNPN
スイツチ23のブレツクダウン電圧に達すると、
2端子PNPNスイツチ23はオンとなり、コンデ
ンサ22の充電電荷は出力トランス24の一次側
を通して放電する。そして、コンデンサ22とト
ランス24の一次コイルとの直列共振は、2端子
PNPNスイツチ23とダイオード2bの逆並列接
続の故に、往復の振動回路が形成されているの
で、何らの支障なく持続され、トランス24の2
次側出力のスパークギヤツプ25にスパークエネ
ルギを供給する。しかし、第1図の従来の装置の
第2図回路の使用例においては、ダイオード素子
2aと2b間の分離が完全でないため、寄生的な
トランジスタ効果、すなわち、P層2aから共通
N層1に注入されたホールが、P層2bとN層1
間のPN接合の逆電界に吸いとられてP層2bに
達するところのPNPトランジスタ動作が起り、所
期の回路動作が得られないことがあつた。
FIG. 2 is an example circuit diagram of the use of two diode elements of the semiconductor device of FIG. 1, and in FIG.
The input AC applied between the terminals A 1 and A 2 through the input transformer 21 charges the capacitor 22 through the element 2a, and the voltage between the terminals of the capacitor 22 becomes K.
2-terminal PNPN connected in parallel between terminal and A 2- terminal
When the breakdown voltage of switch 23 is reached,
The two-terminal PNPN switch 23 is turned on, and the charge in the capacitor 22 is discharged through the primary side of the output transformer 24. The series resonance between the capacitor 22 and the primary coil of the transformer 24 is caused by two terminals.
Because of the anti-parallel connection of the PNPN switch 23 and the diode 2b, a reciprocating oscillation circuit is formed, so it can be maintained without any trouble, and the two of the transformer 24
Spark energy is supplied to the spark gap 25 of the next output. However, in the example of the use of the circuit of FIG. 2 of the conventional device of FIG. The injected holes form the P layer 2b and the N layer 1.
In some cases, the operation of the PNP transistor reaching the P layer 2b was absorbed by the reverse electric field of the PN junction between the two, and the expected circuit operation could not be obtained.

本発明の目的は、上述のダイオード同志間の結
合による寄生トランジスタ効果を起さない、複数
のダイオードが一つのペレツトに組合された半導
体装置を提供するにある。
An object of the present invention is to provide a semiconductor device in which a plurality of diodes are combined into one pellet, which does not cause the parasitic transistor effect due to the coupling between the diodes.

第3図は本発明の半導体装置であり、本発明で
は、第1図のチヤンネルストツパ5が設けられた
位置に、比較的深いP型素子間分離層6とその両
側に浅い高濃度N+不純物層7が設けられ、か
つ、素子間分離層6とN+層7は、その上面に
て、金属電極8により短絡接続されている。
FIG. 3 shows a semiconductor device of the present invention. In the present invention, a relatively deep P-type element isolation layer 6 is provided at the position where the channel stopper 5 of FIG. 1 is provided, and a shallow high-concentration N + An impurity layer 7 is provided, and the inter-element isolation layer 6 and the N + layer 7 are short-circuited by a metal electrode 8 on their upper surfaces.

この第3図に示す本発明の半導体装置では、P
層2aからN層1に注入され、共通N層1を拡散
によりP層2b方向へ向つたホールは、途中の素
子間分離P層6に捕獲され、さらに、ここのPN
接合は上面において短絡されているので、この短
絡部を通してP型素子間分離層6に侵入する電子
により中和されて消滅する。したがつて、第1図
の例のようなP層2bに達するホールはないの
で、寄生トランジスタ効果は発生せず、ダイオー
ド素子2a,2bはお互いに独立に働らき、第2
図のような回路に適用されても、何らこの回路動
作に支障を及ぼさない。
In the semiconductor device of the present invention shown in FIG.
Holes injected from the layer 2a into the N layer 1 and directed toward the P layer 2b by diffusion through the common N layer 1 are captured by the element isolation P layer 6 on the way, and further
Since the junction is short-circuited at the upper surface, it is neutralized and disappears by electrons that enter the P-type element isolation layer 6 through this short-circuited portion. Therefore, since there are no holes that reach the P layer 2b as in the example of FIG.
Even if it is applied to a circuit as shown in the figure, it will not affect the operation of this circuit in any way.

なお、上述の素子間分離層6を形成するには、
例えば、P層2a,2bを形成するときに同時に
形成し、N+層7は、表面シリコン酸化膜上にリ
ンガラス層を形成するのと同時に、また、P型素
子間分離層6とN+層7との間にPN接合短絡のた
めの金属電極8も、アノード電極4a,4b……
…の形成と同時に実施できるので、従来の製造工
程に対し、特別な工数増加なしにできる。
In addition, in order to form the above-mentioned element isolation layer 6,
For example, the N + layer 7 is formed at the same time as the P layers 2a and 2b are formed, and the N + layer 7 is formed at the same time as the phosphorus glass layer is formed on the surface silicon oxide film, and the N The metal electrode 8 for PN junction short circuit between the layer 7 and the anode electrodes 4a, 4b...
Since it can be carried out at the same time as the formation of..., it can be done without any special increase in man-hours compared to the conventional manufacturing process.

このようにして得られた本発明の半導体装置
は、寄生トランジスタ効果を防ぐため、従来ダイ
オード素子間の距離を広くとつていたのに対し、
この距離を狭くしても寄生トランジスタ効果を防
げるので、ダイオード素子間距離を狭くすること
により一つのペレツトの面積を小さくできるの
で、ウエーハ一枚当りのペレツトの収率を上げ原
価を安くすることができる。また、高濃度N+
純物層はホールを消滅させるだけでなく、ダイオ
ード素子間のチヤンネルストツパとしても有効に
働らく。このように、本発明による半導体装置
は、同一ペレツト内の素子間結合を防止されてい
るのみならず、小形化されているので、原価低減
にも役立つという優れた効果を奏する。
In the semiconductor device of the present invention thus obtained, the distance between the diode elements was conventionally set wide in order to prevent parasitic transistor effects.
Even if this distance is narrowed, parasitic transistor effects can be prevented, so by narrowing the distance between diode elements, the area of one pellet can be reduced, increasing the yield of pellets per wafer and lowering the cost. can. Furthermore, the high concentration N + impurity layer not only annihilates holes, but also works effectively as a channel stopper between diode elements. As described above, the semiconductor device according to the present invention not only prevents coupling between elements within the same pellet, but also has a small size, which has an excellent effect of helping to reduce costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の同一ペレツトに2個のダイオー
ド素子を含む半導体装置の断面図、第2図は、第
1図の半導体装置の寄生トランジスタ効果を説明
するための使用例回路図、第3図は本発明の一実
施例の断面図である。 1……N型基板(ペレツト)、2a,2b……
ダイオード素子またはPアノード層、3……シリ
コン酸化膜、4a,4b……金属電極、6……素
子間分離P層、7……チヤンネルストツパ兼コン
タクトN+層、8……分離P層短絡電極。
Fig. 1 is a cross-sectional view of a conventional semiconductor device including two diode elements in the same pellet, Fig. 2 is a usage example circuit diagram for explaining the parasitic transistor effect of the semiconductor device of Fig. 1, and Fig. 3 1 is a sectional view of one embodiment of the present invention. 1...N-type substrate (pellet), 2a, 2b...
Diode element or P anode layer, 3... Silicon oxide film, 4a, 4b... Metal electrode, 6... Element isolation P layer, 7... Channel stopper/contact N + layer, 8... Isolation P layer short circuit electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 一導電型半導体基板に複数の逆導電型領域が
形成された半導体装置において、前記逆導電型領
域間に比較的深い逆導電型の素子分離層および該
素子分離層とPN接合を形成する比較的浅い高不
純物濃度の一導電型層を有し該PN接合が金属電
極により短絡されていることを特徴とする半導体
装置。
1 Comparison of a semiconductor device in which a plurality of regions of opposite conductivity type are formed on a semiconductor substrate of one conductivity type, in which a relatively deep element isolation layer of opposite conductivity type is formed between the regions of opposite conductivity type, and a PN junction is formed with the element isolation layer. 1. A semiconductor device comprising a single conductivity type layer with a shallow high impurity concentration, the PN junction being short-circuited by a metal electrode.
JP12182878A 1978-10-02 1978-10-02 Semiconductor device Granted JPS5548958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12182878A JPS5548958A (en) 1978-10-02 1978-10-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12182878A JPS5548958A (en) 1978-10-02 1978-10-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5548958A JPS5548958A (en) 1980-04-08
JPS6146972B2 true JPS6146972B2 (en) 1986-10-16

Family

ID=14820925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12182878A Granted JPS5548958A (en) 1978-10-02 1978-10-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5548958A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893291A (en) * 1981-11-30 1983-06-02 Fuji Electric Corp Res & Dev Ltd Diode for integrated circuit
US4483472A (en) * 1983-03-01 1984-11-20 Gerber Scientific Inc. Apparatus and method for indexing sheet material
JPS6165060U (en) * 1984-10-05 1986-05-02
JPS62204357U (en) * 1986-06-18 1987-12-26
JP2729062B2 (en) * 1987-10-27 1998-03-18 日本電気株式会社 Integrated circuit device
JP5196794B2 (en) * 2007-01-29 2013-05-15 三菱電機株式会社 Semiconductor device
JP7022022B2 (en) * 2018-07-12 2022-02-17 本田技研工業株式会社 Sheet body cutting method and its cutting device

Also Published As

Publication number Publication date
JPS5548958A (en) 1980-04-08

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