JPS6147017B2 - - Google Patents
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- Publication number
- JPS6147017B2 JPS6147017B2 JP57111061A JP11106182A JPS6147017B2 JP S6147017 B2 JPS6147017 B2 JP S6147017B2 JP 57111061 A JP57111061 A JP 57111061A JP 11106182 A JP11106182 A JP 11106182A JP S6147017 B2 JPS6147017 B2 JP S6147017B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- terminal
- output
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
Description
【発明の詳細な説明】
本発明は集積回路の出力部に関し、特にFM復
調回路の復調出力部に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output section of an integrated circuit, and more particularly to a demodulation output section of an FM demodulation circuit.
集積回路に入力された信号は内部の信号処理回
路により処理され、所望の出力信号が負荷抵抗に
現われるが、集積回路内部での電流変化により不
所望な出力が現われることがある。これは、信号
処理回路の動作の一部を切り換える電子的切換回
路が内蔵されているときに顕著になる。切換回路
を含む集積回路装置はFM復調回路やスケルチ回
路をはじめ各種自動切換回路およびその表示回路
等として多く用いられている。 A signal input to the integrated circuit is processed by an internal signal processing circuit, and a desired output signal appears at the load resistor, but an undesired output may appear due to current changes within the integrated circuit. This becomes noticeable when an electronic switching circuit that switches part of the operation of the signal processing circuit is included. Integrated circuit devices including switching circuits are often used as FM demodulation circuits, squelch circuits, various automatic switching circuits, and their display circuits.
切換回路の動作等により内部電流がかわつて雑
音が発生すると、アナログ信号の質を悪化させて
いる。具体的には音声信号を扱う回路の場合、ス
ピーカ等から耳ざわりなシヨツク音として出力さ
れ不快なばかりでなく、時としてはスピーカを破
壊することもある。テレビジヨンの場合には画面
のみだれとなる。 When the internal current is changed due to the operation of the switching circuit and noise is generated, the quality of the analog signal deteriorates. Specifically, in the case of a circuit that handles audio signals, this noise is output as a harsh shock sound from a speaker, etc., which is not only unpleasant, but may even damage the speaker. In the case of television, the screen becomes blurred.
この原因を追求してみると、切換回路が直接に
アナログ信号を断続する際に重畳する直流分も断
続し、このために直流分の変化を生じてそれが結
合コンデンサで微分され、後段で増幅され出力さ
れる場合と、間接的に、例えば回路の共通布線を
流れる電流の変化が布線抵抗や電源の内部抵抗に
電圧変化を生じ、それがアナログ信号を扱う回路
に影響する場合があることがわかつた。本発明は
後者の解決に関するものである。 When we investigated the cause of this, we found that when the switching circuit directly intermittents the analog signal, the superimposed DC component also intermittents, resulting in a change in the DC component, which is differentiated by the coupling capacitor and amplified in the subsequent stage. For example, a change in the current flowing through the common wiring of a circuit may cause a voltage change in the wiring resistance or the internal resistance of the power supply, which may affect the circuit that handles analog signals. I found out. The present invention relates to the latter solution.
第1図は従来のFMステレオ放送マルチプレツ
クス復調器のブロツク図である。1は電源でその
内部抵抗および布線にともなう抵抗(等価的に2
で示される)を介し、集積回路装置4の外形上
(リードフレーム上)の電源端子5に加えられ
る。又電源1は交流分に対しては、コンデンサ3
でバイパスされている。端子5に加えられた電圧
は引き出し線(ボンデイングワイヤ)等に存在す
る微少抵抗(等価的に6で示される)を介して集
積回路基板上の引き出し用端子(ボンデイング・
パツト)7に加えられ、集積回路内の各ブロツク
の電源として供給される。同様に接地端子につい
ても集積回路基板上の引き出し用端子8から布線
に伴う抵抗(等価的に9で示される)および外形
上の端子10を経て接地される。一方、FM検波
された信号11は結合コンデンサ12を介して入
力端子13(この部分も正しくは外形上の端子と
基板上の端子とにわけられるが、本発明に直接か
かわりあいないので後者を省略した)から集積回
路装置内のエミツタホロア回路15に加えられ、
その出力は復調回路16と副搬送波再生回路23
とにそれぞれ加えられる。復調回路16では、再
生された副搬送波とエミツタホロア回路15の出
力信号との掛算を行い、外形上の端子17,18
を経て負荷抵抗19,21の両端に復調出力を得
る。尚、コンデンサ20,22はデエンフアシス
用である。ここで、搬送波再生回路23はパイロ
ツト信号を2逓倍するが、その際に集積回路に内
蔵できない部品25,27および28があり、こ
れらの部品は電源および接地端子5,10を介さ
ずに電源1に接続され、又は接地される経路をも
つている。29はパイロツト信号の有無あるいは
手動でステレオ・モノラル切替や表示ランプ31
を駆動する電子的切換回路である。33,34は
次段への信号出力端子である。又14は電圧安定
化回路である。 FIG. 1 is a block diagram of a conventional FM stereo broadcast multiplex demodulator. 1 is the power supply, its internal resistance and the resistance associated with wiring (equivalently 2
) is applied to the power supply terminal 5 on the external shape (on the lead frame) of the integrated circuit device 4 . Also, power supply 1 has capacitor 3 for AC component.
is bypassed. The voltage applied to the terminal 5 is applied to the lead-out terminal (bonding wire) on the integrated circuit board via a minute resistance (equivalently indicated by 6) present in the lead-out wire (bonding wire), etc.
7 and is supplied as a power source to each block in the integrated circuit. Similarly, the ground terminal is grounded from the lead-out terminal 8 on the integrated circuit board through a resistance associated with wiring (equivalently indicated by 9) and a terminal 10 on the outside. On the other hand, the FM detected signal 11 is passed through a coupling capacitor 12 to an input terminal 13 (correctly, this part can be divided into a terminal on the outside and a terminal on the board, but the latter is omitted because it is not directly related to the present invention. ) to the emitter follower circuit 15 in the integrated circuit device,
Its output is transmitted to the demodulation circuit 16 and the subcarrier regeneration circuit 23.
and are added to each. The demodulation circuit 16 multiplies the reproduced subcarrier and the output signal of the emitter follower circuit 15, and outputs terminals 17 and 18 on the outer shape.
A demodulated output is obtained at both ends of load resistors 19 and 21. Note that the capacitors 20 and 22 are for de-emphasis. Here, the carrier wave regeneration circuit 23 doubles the pilot signal, but at this time there are components 25, 27 and 28 that cannot be built into the integrated circuit, and these components are connected to the power supply 1 without going through the power supply and ground terminals 5 and 10. It has a path that is connected to or grounded. 29 indicates whether there is a pilot signal or manually switches between stereo and monaural, and an indicator lamp 31
This is an electronic switching circuit that drives the 33 and 34 are signal output terminals to the next stage. Further, 14 is a voltage stabilizing circuit.
かかる回路構成では、切換回路29が切換わる
たびに雑音を発生し、後段(図示せず)で増幅さ
れスピーカから不快な音を発生する。この原因の
1つは、集積回路装置においてはその構造上基板
上の引き出し用端子7,8から細い線で外形上の
端子5,10へ引きださねばならず、そのため、
微少抵抗6,9が存在し、かつ切換の前後で電源
から副搬送波再生回路23、切換回路29等に供
給される電流の直流分に差があり、端子24,2
6を流れる電流の直流分にも差があり、この結
果、電源端子5や接地端子10に流れる電流の直
流分に差を生じて微少抵抗2,6,9等に生ずる
電圧が変動するためである。今、その抵抗値を
0.5Ωとして切換前後で10〜100mAの電流変化が
あるとすれば、数10mVppの電圧変化が生ずるこ
とになる。 In such a circuit configuration, noise is generated every time the switching circuit 29 switches, and the noise is amplified in a subsequent stage (not shown), producing unpleasant sound from the speaker. One of the reasons for this is that, due to the structure of the integrated circuit device, it is necessary to lead out the lead-out terminals 7 and 8 on the board to the terminals 5 and 10 on the outside using thin wires.
There are minute resistances 6 and 9, and there is a difference in the DC component of the current supplied from the power supply to the subcarrier regeneration circuit 23, switching circuit 29, etc. before and after switching, and the terminals 24 and 2
There is also a difference in the DC component of the current flowing through the power supply terminal 5 and the ground terminal 10, which causes a difference in the DC component of the current flowing through the power terminal 5 and the ground terminal 10, and the voltage generated across the microresistors 2, 6, 9, etc. fluctuates. be. Now, the resistance value
If there is a current change of 10 to 100 mA before and after switching at 0.5Ω, a voltage change of several tens of mVpp will occur.
電源側の微少抵抗の影響を考えると、電源の内
部抵抗2による電圧降下の変動によつて端子33
および34と接地との間の直流電圧がそのまま変
動する。なぜなら、基板上の引き出し用端子7の
電圧が多少変動しても電圧安定化回路14のため
に端子17,18を流れる電流はほぼ一定に保た
れるので、これらの電流による抵抗19,21の
両端の電圧はほぼ一定となるからである。いいか
えると、電源の内部抵抗2に生ずる電圧の変化が
そのまま出力端子33,34と接地の間に現れる
のである。これらの電圧変化の和が結合コンデン
サ等で微分され端子33,34の後につく40dB
以上の利得をもつ増幅回路で増幅されるため、ス
ピーカには不快音を出すに十分な電圧がかかるこ
とになる。 Considering the influence of the minute resistance on the power supply side, the voltage drop at terminal 33 due to fluctuations in voltage drop due to internal resistance 2 of the power supply
And the DC voltage between 34 and ground continues to fluctuate. This is because even if the voltage at the lead-out terminal 7 on the board fluctuates somewhat, the current flowing through the terminals 17 and 18 is kept almost constant due to the voltage stabilizing circuit 14, so that the resistances 19 and 21 due to these currents are This is because the voltage at both ends is approximately constant. In other words, the voltage change occurring in the internal resistance 2 of the power supply appears directly between the output terminals 33, 34 and the ground. The sum of these voltage changes is differentiated by a coupling capacitor, etc., and the 40 dB is added after terminals 33 and 34.
Since the signal is amplified by an amplifier circuit with a gain higher than that, a voltage sufficient to produce an unpleasant sound is applied to the speaker.
本発明の目的は、集積回路に流れる電流の変化
により電源インピーダンスで発生する電圧変動が
出力信号に現われるのを防止した集積回路を提供
することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit that prevents voltage fluctuations caused by power source impedance from appearing in output signals due to changes in the current flowing through the integrated circuit.
本発明によれば、信号処理回路の出力信号をカ
レントミラー回路により電流変化し、その電流を
一端が基準電位(接地電位)に接続されている負
荷抵抗へ供給し、この負荷抵抗に得られる信号を
出力信号として出力する集積回路を得る。 According to the present invention, the output signal of the signal processing circuit is changed in current by a current mirror circuit, the current is supplied to a load resistor whose one end is connected to a reference potential (ground potential), and the signal obtained at this load resistor is Obtain an integrated circuit that outputs as an output signal.
本発明では信号がカレントミラー回路へ一度供
給され、この電流増幅率は素子の形状によつて決
められて電源の変動は受けず、しかもカレントミ
ラー回路を介する電流は一端が基準電位点に接続
された負荷抵抗に供給されて出力として取り出さ
れる。従つて、電源インピーダンスによる電源電
圧の変動は受けかたく、雑音の発生は抑えられ
る。 In the present invention, the signal is once supplied to the current mirror circuit, and the current amplification factor is determined by the shape of the element and is not affected by fluctuations in the power supply.Moreover, one end of the current passing through the current mirror circuit is connected to a reference potential point. It is supplied to a load resistor and taken out as an output. Therefore, fluctuations in power supply voltage due to power supply impedance are not easily affected, and noise generation can be suppressed.
以下図面を参照して本発明を詳細に説明する。 The present invention will be described in detail below with reference to the drawings.
第2図は本発明を適用してなるFMステレオ放
送マルチプレツクス復調器のブロツク図であり、
第3図はその詳細な回路図である。同一記号をつ
けているのは同一のものを示している。401〜
409は電圧安定化回路14を構成する素子であ
り、トランジスタ402および404のエミツタ
電圧を一定の値にする。410〜415はエミツ
タホロア回路15を構成しており、端子13から
の入力信号をインピーダンス変換して復調回路1
6と副搬送波再生回路23とに与えている。46
7は外付コンデンサ468を接続する端子であ
る。416〜426は集積回路で広く用いられて
いるスイツチング型の復調回路16を構成する素
子である。431〜444は副搬送波再生回路2
3を構成する素子で、トランジスタ439で入力
信号を増幅し外付の同調回路25でパイロツト信
号を選択してトランジスタ434,436でC級
増幅し、ダイオード443〜444で整形してト
ランジスタ441で2逓倍して外付の38KHZ同
調回路464に再生副搬送波を得てる。パイロツ
ト信号の一部はトランジスタ438によつて整流
されてスイツチング回路29に加えられる。端子
465に接続されるコンデンサ466で平滑され
(ここは手動によるステレオモノラル切替スイツ
チ467の接続端子でもある)、449〜453
で構成されるシユミツトトリガ回路に加えられ、
その出力でランプドライバー454〜456を駆
動してランプ31を点滅させるとともにトランジ
スタ446に加えられ副搬送波再生回路23を動
作又は不動作に切替える。 FIG. 2 is a block diagram of an FM stereo broadcast multiplex demodulator to which the present invention is applied.
FIG. 3 is a detailed circuit diagram thereof. The same symbols indicate the same thing. 401~
Reference numeral 409 denotes an element constituting the voltage stabilizing circuit 14, which keeps the emitter voltages of the transistors 402 and 404 at a constant value. 410 to 415 constitute an emitter follower circuit 15, which converts the input signal from the terminal 13 into impedance and converts it into the demodulation circuit 1.
6 and the subcarrier regeneration circuit 23. 46
7 is a terminal to which an external capacitor 468 is connected. 416 to 426 are elements constituting a switching type demodulation circuit 16 widely used in integrated circuits. 431 to 444 are subcarrier regeneration circuits 2
The transistor 439 amplifies the input signal, the external tuning circuit 25 selects the pilot signal, the transistors 434 and 436 perform class C amplification, the diodes 443 to 444 shape the signal, and the transistor 441 amplifies the input signal. It is multiplied and a reproduced subcarrier wave is obtained by an external 38KHZ tuning circuit 464. A portion of the pilot signal is rectified by transistor 438 and applied to switching circuit 29. It is smoothed by a capacitor 466 connected to a terminal 465 (this is also a connection terminal for a manual stereo monaural changeover switch 467), and 449 to 453.
In addition to the Schmitt trigger circuit consisting of
The output drives the lamp drivers 454 to 456 to blink the lamp 31, and is applied to the transistor 446 to switch the subcarrier regeneration circuit 23 into operation or non-operation.
第1図との大きな違いは、復調回路16の出力
取出構成である。すなわち、復調回路16の一方
の出力(左チヤンネル出力)は、ダイオード35
1、トランジスタ352および抵抗427,42
8でなるカレントミラー回路で電流に変換され、
その電流は一端が接地端子308へ接続された負
荷抵抗319へ供給される。抵抗319の他端が
出力端子317へ接続される。同様に、復調回路
16の他方の出力(右チヤンネル出力)は、ダイ
オード353、トランジスタ354、抵抗42
9,430でなるカレントミラー回路へ供給され
て電流変換され、一端が接地端子308へ他端が
出力端子318へ接続された負荷抵抗321へそ
の電流が供給される。 The major difference from FIG. 1 is the output extraction configuration of the demodulation circuit 16. That is, one output (left channel output) of the demodulation circuit 16 is connected to the diode 35.
1. Transistor 352 and resistors 427, 42
It is converted into a current by a current mirror circuit consisting of 8,
The current is supplied to a load resistor 319 connected at one end to ground terminal 308. The other end of resistor 319 is connected to output terminal 317. Similarly, the other output (right channel output) of the demodulation circuit 16 is connected to the diode 353, the transistor 354, and the resistor 42.
The current is supplied to a current mirror circuit consisting of 9,430 and converted into a current, and the current is supplied to a load resistor 321 whose one end is connected to the ground terminal 308 and the other end is connected to the output terminal 318.
かかる構成において、復調器16の出力電流
は、従来と同様に電圧安定化回路14によつてバ
イアスを安定化されているため、電源電圧が変動
しても直流的にも交流的にもほぼ一定である。ま
た、同一基板上につくられたダイオード351,
353とトランジスタ352,354はエミツタ
面積比で決まる一定の電流増幅率をもつので、負
荷319,321には復調器16の出力電流に比
例した電圧が発生する。これは電源電圧の変動に
対して不感である。したがつて、切換時に電源1
の内部抵抗2や微少抵抗6によつて端子5や引き
出し用端子7の電位が変化しても従来のような出
力端子33,34の電圧の直流分の変化を生ずる
ことはない。317,318は外形上の出力端子
320,322はデエンフアシス用コンデンサで
ある。こうして切換時の雑音の発生を少なくする
ことができた。 In this configuration, the bias of the output current of the demodulator 16 is stabilized by the voltage stabilization circuit 14 as in the conventional case, so even if the power supply voltage fluctuates, the output current remains almost constant in both DC and AC. It is. In addition, a diode 351 made on the same substrate,
Since the transistors 353 and the transistors 352 and 354 have a constant current amplification factor determined by the emitter area ratio, a voltage proportional to the output current of the demodulator 16 is generated in the loads 319 and 321. This is insensitive to fluctuations in power supply voltage. Therefore, when switching, power supply 1
Even if the potentials of the terminal 5 and the lead-out terminal 7 change due to the internal resistance 2 and microresistance 6, the DC component of the voltage of the output terminals 33 and 34 does not change as in the conventional case. Output terminals 320 and 322 on the outside are de-emphasis capacitors 317 and 318, respectively. In this way, it was possible to reduce the noise generated during switching.
尚、出力電圧の直流分は定電圧素子の動抵抗等
のため、若干の電源電圧依存性をもつているが、
実際には電源電圧変動の1/30程度の変動なので電
源1の内部抵抗2に生ずる電圧変動の1/30が切換
時に出力に生じてしまうが、十分小さいので無視
できる。 Note that the DC component of the output voltage has some dependence on the power supply voltage due to the dynamic resistance of the constant voltage element, etc.
In reality, the fluctuation is about 1/30 of the power supply voltage fluctuation, so 1/30 of the voltage fluctuation occurring in the internal resistance 2 of the power supply 1 occurs in the output at the time of switching, but it is sufficiently small and can be ignored.
また、第2,3図に示されるように接地端子が
二つ308,355設けられている。これは、切
換回路29の動作により接地ラインの電位が変動
するを防止したものである。すなわち、信号入力
は信号源11、コンデンサ12、端子13、エミ
ツタホロア回路15、接地用の引き出し端子30
8(その抵抗は等価的に309で示す)、端子3
10を介して信号源にもどる閉回路をなすが、微
少抵抗309に流れる電流が実用上ステレオ、モ
ノラル切換の前後で変化しないようにしているた
め、かかる抵抗の両端の電圧は一定で、入力を介
して切換回路が影響することはない。具体的に
は、かかる抵抗には電圧安定化回路14、エミツ
タホロア15、復調回路16、負荷319,32
1に流れる電流と副搬送波再生回路23の初段の
トランジスタ439のエミツタ電流を流ししてい
るだけで切換動作によつていずれも変化しない。
のこりの部分は第2の接地引き出し端子355
(等価抵抗356)および外形端子357を介し
て接地しているので、接地引き出し端子356の
電位は切換ごとに変化することになるが、副搬送
波再生回路23と切換回路29の接続は基板上で
閉回路をなすようにしてあるため、かかる回路の
動作は電位の多少の変動には依存しない。 Further, as shown in FIGS. 2 and 3, two ground terminals 308 and 355 are provided. This prevents the potential of the ground line from fluctuating due to the operation of the switching circuit 29. That is, the signal input is a signal source 11, a capacitor 12, a terminal 13, an emitter follower circuit 15, and a grounding terminal 30.
8 (its resistance is equivalently designated 309), terminal 3
The current flowing through the microresistance 309 does not change before and after switching between stereo and monaural, so the voltage across the resistor is constant, and the input The switching circuit has no influence through the switching circuit. Specifically, such a resistor includes a voltage stabilizing circuit 14, an emitter follower 15, a demodulating circuit 16, and loads 319 and 32.
1 and the emitter current of the first-stage transistor 439 of the subcarrier regeneration circuit 23 are flowing, and neither of them changes due to the switching operation.
The remaining part is the second ground lead-out terminal 355
(equivalent resistance 356) and the external terminal 357, the potential of the grounding terminal 356 changes every time the subcarrier regeneration circuit 23 and the switching circuit 29 are connected on the board. Since a closed circuit is formed, the operation of such a circuit does not depend on slight fluctuations in potential.
以上のように本発明によれば、電源インピーダ
ンスによる電圧変動の影響を受けない回路とする
ことができる。切換時の直流成分の変化が問題で
あつて、交流成分の変化は通常電源のバイパスコ
ンデンサ(第1図および第3図の3)で吸収され
てしまうので問題とはならない。ただし切換時に
過度的な電流が流れる、例えばコンデンサの充放
電等がある場合には直流成分が過渡的に生じてい
ることになるからこれらの電流を上記のアナログ
信号系の接地用引き出し線を流してはならない。 As described above, according to the present invention, it is possible to provide a circuit that is not affected by voltage fluctuations due to power source impedance. Changes in the DC component during switching are a problem, but changes in the AC component are not a problem because they are usually absorbed by the bypass capacitor (3 in FIGS. 1 and 3) of the power supply. However, if excessive current flows during switching, for example when a capacitor is charged or discharged, a DC component will be generated transiently, so these currents should be passed through the ground lead wire of the analog signal system mentioned above. must not.
第1図は従来のFMステレオ放送マルチプレツ
クス復調器のブロツク図の例、第2図は本発明を
適用してなるFMステレオ放送復調器のブロツク
図の一例、第3図は第2図の詳細な回路図であ
る。
1は電源、2はその内部抵抗を等価的に示した
もの、4は集積回路装置、6および9はそれぞれ
電源および接地用引き出し線の抵抗を等価的に示
したもの、7および8は同様に基板上の引き出し
用端子(ボンデイング・パツド)、5および10
は外形上(リードフレーム上)の端子、14は電
圧安定化回路、15はエミツタホロア回路、16
は復調回路、23は副搬送波再生回路、29は切
替回路、20および22は負荷抵抗、31はラン
プ、33および34は次段への信号出力端子であ
る。
Fig. 1 is an example of a block diagram of a conventional FM stereo broadcast multiplex demodulator, Fig. 2 is an example of a block diagram of an FM stereo broadcast demodulator to which the present invention is applied, and Fig. 3 is a detail of Fig. 2. This is a circuit diagram. 1 is a power supply, 2 is an equivalent representation of its internal resistance, 4 is an integrated circuit device, 6 and 9 are equivalent representations of the resistance of the power supply and ground lead wires, and 7 and 8 are equivalent representations of the resistance. Extraction terminals (bonding pads) on the board, 5 and 10
14 is a voltage stabilizing circuit, 15 is an emitter follower circuit, 16 is a terminal on the outer shape (on a lead frame), and 15 is an emitter follower circuit.
23 is a demodulation circuit, 23 is a subcarrier regeneration circuit, 29 is a switching circuit, 20 and 22 are load resistors, 31 is a lamp, and 33 and 34 are signal output terminals to the next stage.
Claims (1)
位供給端子の間に接続され前記信号処理回路の動
作を制御信号に応答して切換える切換回路とを有
する集積回路装置であつて、前記信号処理回路の
出力端と前記電源供給端子との間に結合され前記
信号処理回路からの出力信号電流を受けてこれに
応じた信号電流を発生するカレントミラー回路
と、このカレントミラー回路の出力端と前記基準
電位供給端子との間に接続された負荷抵抗と、信
号出力端子と、前記負荷抵抗に得られる信号を前
記信号出力端子に供給する手段とをさらに有する
ことを特徴とする集積回路装置。1. An integrated circuit device comprising a signal processing circuit and a switching circuit connected between a power supply terminal and a reference potential supply terminal and switching the operation of the signal processing circuit in response to a control signal, the integrated circuit device comprising: a current mirror circuit coupled between an output terminal and the power supply terminal and receiving an output signal current from the signal processing circuit and generating a corresponding signal current; an output terminal of the current mirror circuit and the reference potential; An integrated circuit device further comprising: a load resistor connected between the load resistor and the supply terminal; a signal output terminal; and means for supplying a signal obtained at the load resistor to the signal output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11106182A JPS5812432A (en) | 1982-06-28 | 1982-06-28 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11106182A JPS5812432A (en) | 1982-06-28 | 1982-06-28 | Integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5210174A Division JPS5936451B2 (en) | 1974-05-10 | 1974-05-10 | integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5812432A JPS5812432A (en) | 1983-01-24 |
| JPS6147017B2 true JPS6147017B2 (en) | 1986-10-17 |
Family
ID=14551405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11106182A Granted JPS5812432A (en) | 1982-06-28 | 1982-06-28 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5812432A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4911761A (en) * | 1972-05-16 | 1974-02-01 |
-
1982
- 1982-06-28 JP JP11106182A patent/JPS5812432A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5812432A (en) | 1983-01-24 |
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