JPS6147028B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is capable of processing a television signal, such as a simple VTR output, in which the length of a horizontal scanning line (line) fluctuates extremely at a substantially constant position during one field period of the television signal. The invention relates to a phase synchronization method that enables writing to memory without inducing errors.

Conventionally, when the video signal period includes sudden fluctuations in the horizontal synchronization period due to head switching, such as the output television signal of a simple VTR (such as a cassette VTR), errors may occur in the memory depending on the state of the fluctuation. I was letting it happen.

An object of the present invention is to prevent errors from occurring in the memory even if there is a sudden change in the horizontal synchronization period in a television signal. Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a block diagram for explaining an embodiment of the present invention. In FIG. 1, 1 is a first input terminal, which is a television signal input terminal, 2 is a synchronization separation circuit, 3 is an analog-to-digital conversion circuit,
4 is a serial-to-parallel conversion circuit, 5 is a memory, 6 is a parallel-to-serial conversion circuit, 7 is a digital-to-analog conversion circuit, 8 is a television signal output terminal, 9 is a first horizontal/vertical synchronization separation circuit, and 10 is a voltage controlled oscillator. 11 is a first field counter; 12 is a first clock generation circuit;
3 is a first address counter, 14 is an address switching circuit, 15 is a second address counter, 16 is a second clock generation circuit, 17 is a second automatic phase control circuit, 18 is a second field counter, 1
9 is a second horizontal/vertical synchronization separation circuit, and 20 is a second input terminal, which is an input terminal for an output side synchronization signal. FIG. 2 is a signal diagram of each signal for explaining an embodiment of the present invention. In FIG. 2, A is the output television signal of a simple VTR, and m indicates that the period of the horizontal synchronizing signal fluctuates extremely (becomes shorter) due to head switching. This television signal A is input to the first input terminal 1.
, the synchronization signal in the television signal is separated by the synchronization separation circuit 2, and then the horizontal and vertical synchronization separation circuit 9
As input. On the other hand, the video signal of the television signal A (a in FIG. 2A) from the synchronization separation circuit 2 enters the analog-to-digital conversion circuit 3 and is encoded into a high-speed digital signal. This high-speed digital signal, ie, digital data, is parallelized by the serial/parallel conversion circuit 4 so that it can be written in the memory 5 in a cycle time or longer. Since writing and reading of memory 5 are asynchronous, reading takes priority,
In order to subordinate the writing, the serial/parallel conversion circuit 4
also serves as a buffer memory that waits for input data. In this serial/parallel conversion circuit 4, an address for writing the data into the memory 5 is also written as well as data. By writing data and addresses to the same serial/parallel converter circuit 4 in this way, when the data read from the serial/parallel converter 4 is written to the memory 5, the address of the memory 5 is also read at the same time, so that the data can be accurately read. Data can be written to the specified address. The data read out in parallel from the memory 5 is converted into serial data by a parallel-serial conversion circuit 6, converted into an analog signal by a digital-to-analog conversion circuit 7, and outputted from an output terminal 8 as a television signal.

On the other hand, the horizontal synchronization signal (B in FIG. 2), which is the output of the first horizontal and vertical synchronization separation circuit 9, is supplied to the first automatic phase control circuit 10. The first automatic phase control circuit 10 outputs the voltage controlled oscillator output synchronized with the input horizontal synchronization signal B to a first field counter 11, a first clock generation circuit 12 and a first clock generation circuit 12.
is supplied to the address counter 13 of. A first clock generation circuit 12 generates various timing pulses corresponding to the output of the first automatic phase control circuit 10, and a first address counter 13 inputs an address for writing data into the memory 5 to the first clock. This occurs at a timing corresponding to a frequency based on the output of the automatic phase control circuit 10. The first field counter 11 counts one field section of the television signal at a frequency twice the input horizontal synchronization frequency, and issues a holding command to the first automatic phase control circuit 10 at a constant count number. Further, reading from the memory 5 is performed based on the output synchronization signal from the second input terminal 20. The output synchronization signal from the second input terminal 20 is supplied to a second horizontal/vertical synchronization separation circuit 19 , and the output horizontal synchronization signal is supplied to a second automatic phase control circuit 17 .
The second automatic phase control circuit 17 outputs the oscillation output of the voltage controlled oscillator synchronized with the output horizontal synchronization to the second clock generation circuit 16 and the second address counter 1.
5. Supplied to the second field counter 18. The second clock generation circuit 16 generates the necessary timing pulses on the output side, the second address counter 15 creates an address for reading data from the memory 5, and the second field counter 15 generates an address for reading data from the memory 5.
8 counts the interval of one field of output at a frequency twice as high as the horizontal synchronization frequency on the output side. Note that data writing and reading from the memory 5 is controlled by the address switching circuit 14.

Now, the serial-to-parallel conversion circuit 4 also plays the role of a buffer memory, and its capacity is determined in accordance with the variation range of the horizontal synchronization frequency on the input side.
However, the buffer capacity required for a signal that causes a sudden horizontal synchronization frequency change as shown in A and B in FIG. 1 is enormous. On the other hand, if the capacity is small enough to accommodate normal horizontal sync frequency fluctuations, that is, approximately 0.5%, the capacity is insufficient for sudden horizontal sync frequency changes such as the output television signal A of a simple VTR. However, in a portion m where a sudden change has occurred, the data of this portion m is written incorrectly in the memory, and at the same time, the address written in pair with the data in the serial/parallel conversion circuit 4 is also incorrectly specified. That is, as shown in FIG. 2C, the control voltage C of the voltage controlled oscillator of the first automatic phase control circuit 10, which is generated due to a change in the horizontal synchronization signal period, is as follows.
Since the period of the horizontal synchronizing signal B on the input side changes rapidly with m, a sudden voltage change occurs at time C', causing a sudden large change in the frequency of the voltage controlled oscillator output. In this way, because the address is specified incorrectly, even the data at the address that has already been written correctly is destroyed, causing the memory 5
The output will be in a state in which not only the information on the line where the sudden change occurred but also information on other lines will be destroyed.

In order to prevent this sudden change, the voltage controlled oscillator of the first automatic phase control circuit 10 is activated as shown in FIG. A hold command for holding the control voltage is sent from the first field counter 11 to the first automatic phase control circuit 10. By sending this hold command, the control voltage of the voltage controlled oscillator of the first automatic phase control circuit 10 is held, and even if a sudden change in the horizontal synchronization signal period occurs, the control voltage is maintained as shown by the broken line in FIG. 2C. The oscillation frequency is based on the held voltage, and no sudden changes in the oscillation frequency occur. In this way the first
If the control voltage of the voltage controlled oscillator of the automatic phase control circuit 10 is maintained and the control voltage of the voltage controlled oscillator of the automatic phase control circuit 10 is maintained and the sudden frequency fluctuations are not followed, the information on several lines near where a sudden fluctuation in the horizontal synchronization signal period occurs will be out of phase. Although the data is written to the memory 5 in the current state, the data that has already been written will not be destroyed.

Furthermore, after the control voltage holding period ends, the output of the first automatic phase control circuit 10 (E in Fig. 2) is forced to match the phase as shown by n in E in Fig. 2 using the input horizontal synchronization signal. This can prevent the control voltage from changing suddenly. Note that after a change in the horizontal synchronization signal period occurs, a large phase shift occurs between the television signal and the output phase of the first automatic phase control circuit 10 until the phase is forcibly adjusted. It's only a few lines, so it's not a big problem.

As explained above, according to the present invention, a television signal can be written to a storage device without inducing errors, and after a phase shift occurs, the phase can be quickly adjusted to the input horizontal synchronizing signal. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG. 2 is a signal diagram for explaining an embodiment of the present invention. 1...First input terminal, 2...Synchronization separation circuit,
3...Analog-digital conversion circuit, 4...Serial-parallel conversion circuit, 5...Memory, 6...Parallel-serial conversion circuit, 7...Digital-analog conversion circuit, 8...
Television signal output terminal, 9, 19...Horizontal/vertical synchronization separation circuit, 10, 17...Automatic phase control circuit, 11, 18...Field counter, 1
2, 16... Clock generation circuit, 13, 15...
Address counter, 14...address switching circuit,
20...Second input terminal.

Claims (1)

[Claims] 1 A video signal of a television signal in which extreme fluctuations in the horizontal synchronization signal period due to head switching occur at a nearly constant position within one field, such as the output of a simple VTR, is output from the input television signal. When only the video signal section is encoded and written to memory based on the horizontal synchronization signal of
A control voltage of a voltage controlled oscillator of an automatic phase control circuit that automatically performs phase synchronization with an input horizontal synchronization signal is maintained at a voltage before extreme fluctuations of the input horizontal synchronization signal occur, and based on the maintained voltage. The video signal is encoded and written into the memory at a timing corresponding to the frequency, and after the writing is completed, the control voltage of the voltage controlled oscillator of the automatic phase control circuit is released from being held, and the input horizontal synchronization signal is used to control the automatic phase control circuit. A phase synchronization method characterized in that an output phase is forcibly synchronized with the input horizontal synchronization signal.