JPS6148734B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to microprogrammed control circuits.

Conventional addressing of microprogram storage means is accomplished by two methods described below. In the first method, each microinstruction has a next instruction address field indicating the storage address within the microprogram storage means of the next microinstruction to be read and executed.

Therefore, the capacity of the microprogram storage means increases by the number of bits of the address, and the amount of hardware increases. Next, in the second method, "1" is added to the storage address of the current microinstruction in the microprogram storage means, and the result of the addition is used as the storage address of the next microinstruction to be read and executed. Therefore, in this method, it is difficult to use the storage area in the microprogram storage means effectively because the number of microinstruction steps required for each of the various soft instructions is different, and furthermore, branches occur in the microinstruction sequence. When specifying a branch destination address with a microinstruction, a field in the microinstruction that is normally used for controlling other purposes is used as an address specification field only at this time, so this branch control and storage processing control cannot be performed in the same step.
Therefore, there are disadvantages in that an increase in the number of microinstruction steps causes an increase in the amount of hardware and a decrease in performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control circuit in which the storage area in a microprogram storage means can be easily and effectively utilized and the amount of hardware can be reduced.

The circuit of the present invention includes: a first storage circuit that stores a microprogram consisting of branch microinstructions that control the operation of an information processing circuit; an instruction code storage means that stores an instruction code; and an instruction code storage means that stores an instruction code. a first circuit that adds a predetermined value to an instruction code; and when the microinstruction read from the first storage circuit is a branch microinstruction, the output of the first circuit is selected as the instruction code. and a code selection circuit that selects an instruction code from the instruction code storage means when the microinstruction read out from the first storage circuit is not a branch microinstruction; and a code selection circuit that selects an instruction code from the instruction code storage means; a second storage circuit that stores a microinstruction readout address of the first storage circuit at the address where the microinstruction is read; and a second storage circuit that adds or subtracts a predetermined value to or from the microinstruction readout address of the first storage circuit. a second circuit; when a new instruction code is externally stored in the instruction code storage means, the instruction code is selected and given as a microinstruction reading address of the first storage circuit; Select one of the circuit and the second circuit, and select the first circuit.
and a selection circuit that provides an address for reading microinstructions from the storage circuit.

A feature of the present invention is that the microinstruction sequence corresponding to each soft instruction is arranged in principle in the first storage circuit according to a predetermined rule, and when the second step microinstruction storage address or branch The purpose of this arrangement is to obtain branch destination addresses from the second storage circuit only when they are needed.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the circuit of the present invention comprises a first address decoder 11 given a 10-bit first address 600 and a first memory 12 of 1024 words, and a microinstruction corresponding to the first address 600. A first storage circuit 10 outputs 120, an instruction code register 20 stores an 8-bit instruction code 200 in a soft instruction, a second address decoder 31 receives a 9-bit fourth address 800, and a 512-word x 10-bit A second storage circuit 30 comprising a second memory 32, which outputs a 10-bit second address 320 corresponding to the fourth address, an address addition circuit 40 which adds "1" to the first address 600, and a second storage circuit 30 that outputs a 10-bit second address 320 corresponding to the fourth address; The 10-bit output data 400 of the adder circuit 40 is given, and the 10-bit third
An 8-bit instruction code that is the output of the instruction address register 50 and the instruction code register 20 to be read and executed next after the address 500 is output.
10-bit data with 201 as the lower 8 bits and the upper 2 bits as “00”, 10-bit second address
320 and the 10-bit third address 500, and select the 10-bit first address 600.
An address selection circuit 60 that outputs the above instruction code 201, a code addition circuit 70 that adds "2 ⁸ " to the instruction code 201, a 9-bit addition result 700 in the code addition circuit 70, and the lower 8 bits of the 8-bit instruction code 201. 9 with the top 1 bit as “0”
The code selection circuit 80 selects two types of bit data and outputs the 9-bit fourth address 800.

However, to add "2 ⁸ " to the instruction code 201, it is only necessary to add one bit "1" to the upper side of the 8-bit instruction code 201.

Next, the operation of the present invention will be explained by illustrating the processing of a soft instruction consisting of a microinstruction sequence of three or more steps including a branch instruction.

(1) First step: The instruction code 201 is selected as the first address 600 in the address selection circuit 60, and the first step microinstruction is read as the microinstruction 120 from the first storage circuit 10 by specifying this address 600. issued and executed.

(2) Second step...In the code selection circuit 80, the instruction code 201 is selected and the fourth address 800 is specified.The second address 320 is read out from the second storage circuit 30 according to the specification, and the second address 320 is read out from the address selection circuit 60.
select this second address 320 and
The address is set to 600, and the second step microinstruction is read out from the first storage circuit 10 and executed according to the designation.

(3) Steps after branching when a branch occurs...In the code selection circuit 80, the addition result 700 is
The second address 320 is selected as the address 800, and the second address 320 is read out from the second storage circuit 30 according to the designation, and the second address 320 is selected as the first address 600 in the address selection circuit 60, and the second address 320 is branched from the first storage circuit 10 according to the designation. The previous microinstruction is read and executed.

(4) Other steps...address selection circuit 60
, set “1” to the first address in the previous step.
The third address 500, which is the result of adding
The first storage circuit 10 selected as address 600
The required microinstruction is read and executed.

By adopting the above configuration, conventionally the first storage circuit 10 required an additional 1024 words x 10 bits as the next instruction address field, but in this embodiment, the second storage circuit 30 has 512 words x 10 bits.
This can be achieved using bits, that is, half the amount of metal used in the past.

The present invention has the advantage that a small microprogram control circuit can be realized by using the second storage circuit to specify, for example, the address of a second step microinstruction or a branch destination microinstruction.

[Brief explanation of the drawing]

The figure is a circuit diagram showing one embodiment of the present invention. In the figure, 10...first storage circuit, 11...
First address decoder, 12...first memory, 2
0...Instruction code register, 30...Second storage circuit, 31...Second decoder, 32...Second memory, 40...Address addition circuit, 50...Next instruction address register, 60...Address selection circuit ,
70...Code addition circuit, 80...Code selection circuit.

Claims (1)

[Scope of Claims] 1. A first storage circuit that stores a microprogram consisting of a plurality of microinstructions including a branch microinstruction that controls the operation of an information processing circuit; Instruction code storage means that stores an instruction code; a first circuit that adds a predetermined value to an instruction code given from the instruction code storage means; and when the microinstruction read from the first storage circuit is a branch microinstruction, the first circuit a code selection circuit that selects an output as an instruction code and selects an instruction code from the instruction code storage means when the microinstruction read from the first storage circuit is not a branch microinstruction; a second storage circuit that stores a microinstruction read address of the first storage circuit at an address specified by the instruction code; and a second storage circuit that stores a microinstruction read address of the first storage circuit at an address specified by the instruction code. a second circuit for adding or subtracting a new instruction code from the outside, when a new instruction code is stored in the instruction code storage means, selecting the instruction code and giving it as a microinstruction reading address to the first storage circuit; A microprogram control circuit comprising: the second storage circuit; and a selection circuit that selects one of the second storage circuits and provides it as a microinstruction reading address for the first storage circuit.