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JPS6148752B2 - - Google Patents
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JPS6148752B2 - - Google Patents

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Publication number
JPS6148752B2
JPS6148752B2 JP2448279A JP2448279A JPS6148752B2 JP S6148752 B2 JPS6148752 B2 JP S6148752B2 JP 2448279 A JP2448279 A JP 2448279A JP 2448279 A JP2448279 A JP 2448279A JP S6148752 B2 JPS6148752 B2 JP S6148752B2
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JP
Japan
Prior art keywords
input signal
signal
equation
limit value
coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2448279A
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Japanese (ja)
Other versions
JPS55118183A (en
Inventor
Tsutomu Okayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2448279A priority Critical patent/JPS55118183A/en
Publication of JPS55118183A publication Critical patent/JPS55118183A/en
Publication of JPS6148752B2 publication Critical patent/JPS6148752B2/ja
Granted legal-status Critical Current

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  • Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は、たとえば各種計測信号の信号処理回
路に関し、特に信号の非直線性を補正する信号処
理回路の改良に係る。 一般に、計装システムにおける温度、圧力等の
各種計測信号の被測定量とそれを電気信号に変換
するための信号処理回路の入力信号との間には理
想的な比例関係は存在せず、非直線誤差を持つ。 たとえば、被測定量をXとし、入力信号(一般
には演算増巾器の入力信号)Vioの関係は、第1
図aに示すように理想的な比例関係は得られず、
同図bに示すような非直線誤差を持つている。 このような被測定量Xと入力信号Vioとの関係
の非直線誤差は、高精度の検出が要求される分野
においては、補正をすることが是非とも必要にな
る。 この非直線誤差の補正方法としては従来より折
線近似法による方法と多項式近似法による方法の
2通りのものが提案されている。 第2図は、折線近似法によつて第1図の入力信
号Vioの非直線誤差を補正するための補正信号Y
で、第3図は、同様に多項式近似法によつて発生
した補正信号Yを示す。 まず、第2図に示すような近線近似法による補
正信号Yを演算増巾器を用いて得る場合、良好な
非直線誤差の補正結果を得るには折点数が多数必
要となる。この場合、図上左側0%側から各折線
の傾斜を順次定めていけば、比較的簡単な手順の
繰返しで各折線の傾斜の係数設定を行うことがで
きる。 しかしながら、各折線毎にその折線の傾斜を加
味した折線関数発生回路(演算増巾器を用いた回
路)が必要となり、補正信号Yを得るための回路
構成が複雑となり、部品点数も増加する。 特に入力信号Vioの微係数が単調に増加しない
場合には、折線関数発生回路の出力を反転する等
の余分な調整が必要になつて構成も一層複雑化す
る。 第3図は点線の曲線は、多項式近似法によつて
発生した補正信号の例で、入力信号Vioの2乗項
(≒X2)、3乗項(≒X3)を例えばアナログ乗算器
により発生し、この補正信号成分を係数設定器に
より加減算することによつて得るものである。こ
の方法は係数設定器の数が少なく、回路自体も比
較的簡単であり、設定が適切であれば、高精度な
補正能力を有する。 しかしながらこの方法は、多数個の実測値をも
とに例えば最小自乗法などの繁雑な計算により、
入力信号VioをX,X2,X3等の成分に分けた後、
各項の係数と反対の符号をダイアル設定等の方法
により、必要な係数を一定の数値に設定する必要
がある。従つてVioの各項の成分があらかじめ判
明している場合以外には、測定および計算が繁雑
でしかも係数設定作業が難かしいという欠点があ
る。 本発明の目的は、係数設定器の数が少なく、複
雑な計算を必要とせずに、簡単に短かい手順で係
数設定が行える入力信号の非直線誤差を補正する
ための信号処理回路を提供するにある。 本発明の実施例を説明するのに先立つて、基本
的な考え方について説明する。 一般に非直線性誤差を含む入力信号Vioは次式
のような測定量Xのべき級数で表わすことができ
る。 Vio(X) =a0″+a1″X+a2″X2+a3″X3+a4″X4+ …(1) 本発明は上記べき級数で表わされる信号をその
係数を実測値から直接的に定めることが可能で、
かつ、回路的にも容易に実現できる多項式の和と
して関数を表わしなおすことにより、前述の目的
を達成するものである。 入力信号Vioのゼロと感度が予め調整されてい
るものと仮定すると、Vio(0)=0Vio(1)=1が成
立する。但し測定量は0≦X≦1とする。従つて
(1)式は Vio(X) =a1′X+a2′X2+a3′X3+a4′X4+ …(2)
The present invention relates to, for example, a signal processing circuit for various measurement signals, and particularly to an improvement in a signal processing circuit for correcting signal nonlinearity. Generally, there is no ideal proportional relationship between the measured quantity of various measurement signals such as temperature and pressure in an instrumentation system and the input signal of the signal processing circuit for converting it into an electrical signal. It has a linear error. For example, let the quantity to be measured be X, and the relationship between the input signal (generally the input signal of an operational amplifier) V io is the first
As shown in Figure a, an ideal proportional relationship cannot be obtained;
It has a non-linear error as shown in figure b. Such non-linear errors in the relationship between the measured quantity X and the input signal V io must be corrected in fields where highly accurate detection is required. Conventionally, two methods have been proposed for correcting this non-linear error: a method using a broken line approximation method and a method using a polynomial approximation method. FIG. 2 shows a correction signal Y for correcting the non-linear error of the input signal V io of FIG. 1 using the broken line approximation method.
FIG. 3 shows a correction signal Y similarly generated by the polynomial approximation method. First, when obtaining the correction signal Y by the near-line approximation method as shown in FIG. 2 using an operational amplifier, a large number of break points are required to obtain a good non-linear error correction result. In this case, by sequentially determining the slope of each broken line starting from the 0% side on the left side of the figure, the slope coefficient of each broken line can be set by repeating a relatively simple procedure. However, a broken line function generation circuit (a circuit using an operational amplifier) that takes into account the slope of the broken line is required for each broken line, which complicates the circuit configuration for obtaining the correction signal Y and increases the number of parts. Particularly when the differential coefficient of the input signal V io does not increase monotonically, extra adjustments such as inverting the output of the polygonal function generating circuit are required, making the configuration even more complicated. In FIG. 3, the dotted curve is an example of a correction signal generated by the polynomial approximation method, and the square term (≒X 2 ) and cube term (≒X 3 ) of the input signal V io are used, for example, by an analog multiplier. This correction signal component is generated by adding and subtracting this correction signal component using a coefficient setter. This method requires a small number of coefficient setters, the circuit itself is relatively simple, and if the settings are appropriate, it has a highly accurate correction ability. However, this method uses complicated calculations such as the method of least squares based on a large number of measured values.
After dividing the input signal V io into components such as X, X 2 , X 3 , etc.,
It is necessary to set the necessary coefficients to a constant value by dialing the opposite sign of the coefficient of each term. Therefore, unless the components of each term of V io are known in advance, measurements and calculations are complicated and the coefficient setting work is difficult. An object of the present invention is to provide a signal processing circuit for correcting non-linear errors in an input signal, which has a small number of coefficient setters and can easily set coefficients in short steps without requiring complicated calculations. It is in. Before explaining embodiments of the present invention, the basic idea will be explained. In general, the input signal V io containing a nonlinearity error can be expressed as a power series of the measured quantity X as shown in the following equation. V io ( X ) = a 0 ″ + a 1X + a 2 ″X 2 + a 3 ″X 3 + a 4 ″ It is possible to define
In addition, the above-mentioned object is achieved by re-expressing the function as a sum of polynomials that can be easily realized in circuit terms. Assuming that the zero and sensitivity of the input signal V io are adjusted in advance, V io (0)=0V io (1)=1 holds true. However, the measured quantity is 0≦X≦1. Accordingly
Equation (1) is V io (X) = a 1 ′X + a 2 ′X 2 + a 3 ′X 3 + a 4 ′X 4 + …(2)

【式】となる性質をもつ。 ここで、Vio(X)=Yとし Y(Y−1) …(3) Y(Y−1/2)(Y−1) …(4) Y(Y−1/4(Y−1/2)(Y−1) …(5) というように以下同様に多項式を求め、これら多
項式の和を求めると(2)式は次式のようになる。 Vio(X)=a1X+a2Y(Y−1) +a3Y(Y−2/1)(Y−1) +a4Y(Y−1/4)(Y−1/2)(Y−1) +…… …(6) 一般に入力信号Vioに含まれる非直線誤差は数
%と小さく、かつ正弦波状的に多数回も蛇行する
ものはほとんどないので、高次項ほど小さな値と
なる。 入力信号Vioにおける主要項は、その係数がほ
ぼ“1”に近い“a1・X”であるから、例えば、
X4項は十分に小さいので、無視できる。 このため、(6)式において、Yを再びXの多項式
で展開した場合、Y(Y−1),Y(Y−1/2)(Y −1),…等の各項から生ずるX4項は、a4′(1−
a1′)と同じ範囲である。 よつて、(6)式のYの3次項a3までによつて入力
信号Vioを近似しても、近似誤差はほとんど生じ
ないと考えてよい。 また、Vio(1)=1であるから、(6)式においてY
=1,X=1とおくと、a1=1となる。 したがつて、(6)式は次のようになる。 Vio(X) =X+Y(Y−1){a2+a3(Y−1/2)} …(7) この(7)式から明らかなようにY項が非直線誤差
に対応するものであるから、入力信号Vioの非直
線誤差を補正した正しい信号VOを得るには、 VO(X)=Vio(X) +Y(Y−1){k+m(Y−1/2)} …(8) とすればよい。 この(8)式が、この発明によつて実現される入力
信号Vioの非直線誤差を補正した正しい信号VO
である。 もちろん、(7)式を(8)式に代入すると、 VO(X)=X+Y(Y−1) {(k+a2)+(m+a3)(Y−1/2)} …(9) となる。 この(9)式に示すとうり、VO(0)=0,VO(1)
=1が成立することは明らかである。 次に(8)式を実現するに際しては、k及びmを係
数設定器で設定する必要がある。それを以下に説
明する。 まずY=1/2となる測定量Xを加える。 1/4(k+a2)=X1−VO(X1) …(10) X1−VO(X1)は理想値からの偏差であるか
ら、係数設定器により偏差が0になるようkを調
整する。 即ち k=−a2 …(11) が成立する。 次に(m+a3)が大となる点、例えばY=1/4とな る測定量を加える。 X2−VO(X2)=3/64(m+a3) …(12) ここで、X2−VO(X2)は理想値からの偏差で
あるから、これを0とするように係数設定器によ
りmを設定し、m=−a3 …(13) とする。このとき VO(X)=X …(14) が0≦X≦1の任意のXで成立する。 以上の説明の通りの本発明は(8)式を実現するこ
とによつて所期の目的を達成するものである。(8)
式に示すように入力信号Vioの補正信号として
は、入力信号の下限値及び上限値近傍で零となる
成分{Y(Y−1)}の関数と、入力信号の下限
値、上限値及び中間値近傍で零となる成分{Y
(Y−1/2)・(Y−1)}の関数の2組の信号を発
生 すればよい。 以下、具体的な実現例である本発明の一実施例
を第4図に示す。第4図はアナログ手段によつて
実現した回路構成を示す図で、第5図はその各部
の特性を示す図である。 第4図、第5図において、抵抗R1,R2、定
電圧源V1および演算増幅器A1からなる加算器
により、第5図aの特性のような(Vio−1/2)の 項を得る。次にアナログ乗算器M1により(Vio
−1/2)項を作り、その出力Y2は第5図のb特性 が得られる。次段の加算器は、演算増幅器A2
と、抵抗R3,R4および定電圧源V2より構成
されており、A2の出力Y2=Vio(Vio−1)が
得られる。(第5図C)B部の乗算器M2では
(Vio−1/2)とA部の出力Vio(Vio−1)の積を
作 りその出力Y3は第5図dの如く、Vio(Vio−1/2) (Vio−1)が得られる。係数設定の便宜をはか
るため、利得−1の演算増幅器を介在させ、係数
設定器VR1,VR2の両端に±Y2および±Y3
それぞれ印加しているので、係数設定器の可変抵
抗を回わすことにより、−1〜0〜1と連続的
に、(8)式における係数k,mを設定できる。 抵抗R5,R6,R7および演算増幅器A5か
らなる加算器により、 VO=Vio+Vio(Vio−1) k+Vio(Vio−1/2)(Vio−1)m を得る。したがつて、Aが入力信号Vioの下限
0、上限1で零となる関数発生部で、Bが入力信
号Vioの下限0、上限1、中間1/2で零となる関数 発生部である。調整作業はVio=1/2において、VO の理想曲線からの偏差が0となるようにVR1を
回わした後、Vio=1/4において、VOの偏差を0と するようVR2を設定するのみである。 実作業においては、X=1/2およびX=1/4点で
VR 1,VR2を設定しても同様良好な結果が得られ
る。本実施例によれば、上述の如く偏差を0にす
るという極めて簡単な調整作業でしかも補正後の
直線性が、多項式近似法と同様に優れたものが得
られる。即ち調整の容易な折線近線似法に比較し
ても数分の1で調整できかつ部品点数は多項式近
似法と同等以下である。 本発明は、各係数設定器により設定される多項
式が、より低次の多項式のすべてと共通因数をも
つことから生じている。従つてより高次の4次、
5次関数等に対しても有効であり、補正手段がア
ナログ・デイジタルであるかに依存せず、本発明
の目的は達成される。 以上、説明したように本発明によれば、簡単な
回路構成で、しかも係数設定の手順も容易な非直
線誤差を有する入力信号を補正する信号処理回路
を得ることができる。
It has the property of [Formula]. Here, V io (X) = Y, Y (Y-1) ... (3) Y (Y-1/2) (Y-1) ... (4) Y (Y-1/4 (Y-1/ 2) (Y-1) ...(5) Similarly, if you calculate the polynomials below and calculate the sum of these polynomials, equation (2) becomes as follows: V io (X) = a 1 X + a 2 Y (Y-1) +a 3 Y (Y-2/1) (Y-1) +a 4 Y (Y-1/4) (Y-1/2) (Y-1) +... ...(6) In general, the non-linear error included in the input signal V io is as small as a few percent, and there is almost no sinusoidal meandering many times, so the higher the order, the smaller the value.The main terms in the input signal V io are: Since the coefficient is “a 1・X” which is almost “1”, for example,
The X4 term is small enough so it can be ignored. Therefore, in equation (6), when Y is expanded again by a polynomial of The term is a 4 ′(1−
a 1 ′). Therefore, it can be considered that almost no approximation error occurs even if the input signal V io is approximated by up to the cubic term a 3 of Y in equation (6). Also, since V io (1)=1, in equation (6), Y
=1 and X=1, then a 1 =1. Therefore, equation (6) becomes as follows. V io (X) = X + Y (Y-1) {a 2 + a 3 (Y-1/2)} ...(7) As is clear from this equation (7), the Y term corresponds to the nonlinear error. Therefore, in order to obtain the correct signal V O that corrects the nonlinear error of the input signal V io , V O (X) = V io (X) + Y (Y-1) {k + m (Y-1/2)} …(8) is sufficient. This equation (8) is the correct signal V O that corrects the nonlinear error of the input signal V io realized by this invention.
It is. Of course, by substituting equation (7) into equation (8), we get V O (X)=X+Y(Y-1) {(k+a 2 )+(m+a 3 )(Y-1/2)}...(9) Become. As shown in this equation (9), V O (0)=0, V O (1)
It is clear that =1 holds true. Next, when realizing equation (8), it is necessary to set k and m using a coefficient setter. This will be explained below. First, add the measured quantity X such that Y=1/2. 1/4 (k+a 2 )=X 1 −V O (X 1 ) …(10) Since X 1 −V O (X 1 ) is the deviation from the ideal value, use the coefficient setter to make the deviation 0. Adjust k. That is, k=-a 2 (11) holds true. Next, add the point where (m+a 3 ) is large, for example, the measured quantity where Y=1/4. X 2 −V O (X 2 )=3/64(m+a 3 ) …(12) Here, since X 2 −V O (X 2 ) is the deviation from the ideal value, set it to 0. Set m using the coefficient setter, m=-a 3 ...(13). At this time, V O (X)=X (14) holds true for any X satisfying 0≦X≦1. The present invention as explained above achieves the intended purpose by realizing equation (8). (8)
As shown in the formula, the correction signal for the input signal V io is a function of the component {Y(Y-1)} that becomes zero near the lower limit value and upper limit value of the input signal, and the lower limit value, upper limit value, and Component that becomes zero near the intermediate value {Y
It is sufficient to generate two sets of signals having functions of (Y-1/2) and (Y-1)}. An embodiment of the present invention, which is a specific implementation example, is shown in FIG. 4 below. FIG. 4 is a diagram showing a circuit configuration realized by analog means, and FIG. 5 is a diagram showing the characteristics of each part thereof. In FIGS. 4 and 5, an adder including resistors R1 and R2, a constant voltage source V1, and an operational amplifier A1 obtains the term (V io -1/2) as shown in the characteristic shown in FIG. 5a. Next, the analog multiplier M1 (V io
-1/2) 2 terms are created, and the output Y 2 has the b characteristic shown in Figure 5. The next stage adder is operational amplifier A2
, resistors R3 and R4, and a constant voltage source V2, and output Y 2 =V io (V io -1) of A2 is obtained. (Fig. 5C) Multiplier M2 in section B multiplies (V io -1/2) and output V io (V io -1) of section A, and the output Y 3 is as shown in Fig. 5d. V io (V io -1/2) (V io -1) is obtained. In order to facilitate coefficient setting, an operational amplifier with a gain of -1 is interposed, and ±Y 2 and ±Y 3 are applied to both ends of coefficient setters VR1 and VR2, respectively. By doing so, the coefficients k and m in equation (8) can be set continuously from -1 to 0 to 1. An adder consisting of resistors R5, R6, R7 and an operational amplifier A5 obtains V 0 =V io +V io (V io -1)k+V io (V io -1/2) (V io -1)m. Therefore, A is a function generating section where the input signal V io becomes zero when the lower limit is 0 and the upper limit is 1, and B is a function generating section where the input signal V io becomes zero when the lower limit is 0, the upper limit is 1, and the middle 1/2. be. The adjustment work is to turn VR1 so that the deviation of V O from the ideal curve becomes 0 at V io = 1/2, and then turn VR2 so that the deviation of V O from the ideal curve becomes 0 at V io = 1/4. Just set the . In actual work, X = 1/2 and X = 1/4 points.
Similar good results can be obtained even if VR 1 and VR 2 are set. According to this embodiment, it is possible to achieve linearity after correction that is as excellent as that of the polynomial approximation method with the extremely simple adjustment work of reducing the deviation to 0 as described above. That is, compared to the easy-to-adjust polygonal line approximation method, the adjustment can be made at a fraction of the cost, and the number of parts is equal to or less than that of the polynomial approximation method. The invention arises from the fact that the polynomial set by each coefficient setter has common factors with all of the lower order polynomials. Therefore, the higher fourth order,
It is also effective for quintic functions, etc., and the object of the present invention can be achieved regardless of whether the correction means is analog or digital. As described above, according to the present invention, it is possible to obtain a signal processing circuit that corrects an input signal having a nonlinear error with a simple circuit configuration and an easy procedure for setting coefficients.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明が適用される入力信号の一
例を示す図、第2図、第3図は従来の入力信号の
非直線誤差の補正方法を説明するための図、第4
図は、本発明の一実施例を示す図、第5図は、そ
の各部特性を示す図である。 A1〜A5……演算増巾器、R1〜R7……抵
抗、VR1,VR2……係数設定器、M1,M2…
…乗算器。
FIG. 1 is a diagram showing an example of an input signal to which the present invention is applied, FIGS. 2 and 3 are diagrams for explaining a conventional method for correcting non-linear errors of input signals, and FIG.
The figure shows an embodiment of the present invention, and FIG. 5 shows the characteristics of each part thereof. A1 to A5...Arithmetic amplifier, R1 to R7...Resistor, VR1, VR2...Coefficient setter, M1, M2...
...multiplier.

Claims (1)

【特許請求の範囲】[Claims] 1 非直線性の入力信号を補正信号で補正して直
線性の出力信号を得るようにしたものにおいて、
前記入力信号の下限値および上限値近傍で零とな
る2次関数を出力する第1関数発生部と、前記入
力信号の下限値、上限値および中間値近傍で零と
なる3次関数を出力する第2関数発生部とを具備
し、両関数発生部の出力を合成して前記補正信号
を得ることを特徴とする信号処理回路。
1 In a device that corrects a nonlinear input signal with a correction signal to obtain a linear output signal,
a first function generating unit that outputs a quadratic function that becomes zero near the lower limit value and the upper limit value of the input signal, and outputs a cubic function that becomes zero near the lower limit value, the upper limit value, and the intermediate value of the input signal. a second function generating section, and combining outputs of both function generating sections to obtain the correction signal.
JP2448279A 1979-03-05 1979-03-05 Signal process circuit Granted JPS55118183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2448279A JPS55118183A (en) 1979-03-05 1979-03-05 Signal process circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2448279A JPS55118183A (en) 1979-03-05 1979-03-05 Signal process circuit

Publications (2)

Publication Number Publication Date
JPS55118183A JPS55118183A (en) 1980-09-10
JPS6148752B2 true JPS6148752B2 (en) 1986-10-25

Family

ID=12139397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2448279A Granted JPS55118183A (en) 1979-03-05 1979-03-05 Signal process circuit

Country Status (1)

Country Link
JP (1) JPS55118183A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104518A (en) * 1986-10-21 1988-05-10 Sony Corp Function generating circuit

Also Published As

Publication number Publication date
JPS55118183A (en) 1980-09-10

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