Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS6149696B2 - - Google Patents
[go: Go Back, main page]

JPS6149696B2 - - Google Patents

Info

Publication number
JPS6149696B2
JPS6149696B2 JP56203269A JP20326981A JPS6149696B2 JP S6149696 B2 JPS6149696 B2 JP S6149696B2 JP 56203269 A JP56203269 A JP 56203269A JP 20326981 A JP20326981 A JP 20326981A JP S6149696 B2 JPS6149696 B2 JP S6149696B2
Authority
JP
Japan
Prior art keywords
stack
internal
internal stack
pointer
external save
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56203269A
Other languages
Japanese (ja)
Other versions
JPS58103043A (en
Inventor
Yoshio Nakano
Masashi Deguchi
Teiji Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56203269A priority Critical patent/JPS58103043A/en
Publication of JPS58103043A publication Critical patent/JPS58103043A/en
Publication of JPS6149696B2 publication Critical patent/JPS6149696B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/448Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482Procedural
    • G06F9/4484Executing subprograms
    • G06F9/4486Formation of subprogram jump address

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Description

【発明の詳細な説明】 本発明は、情報処理装置例えばマイクロコンピ
ユータ装置で、データの受け渡し例えば副プログ
ラム分岐の際の引数や主プログラムへの戻り番地
の格納に使用されるスタツク形成方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stack formation method used in an information processing device, such as a microcomputer device, to transfer data, for example, to store arguments when branching to a subprogram and a return address to a main program. be.

従来例を第1図に示す。演算処理装置1内にス
タツクポインタ2なるものを設け、そのスタツク
ポインタ2の内容が示すアドレスに対応する記憶
装置3内のメモリに対してのみ読み書きができる
機構を形成し、メモリに対して1回読み書きする
ごとにスタツクポインタ2の内容を1語の占める
アドレス領域分例えば1だけ増減することによつ
て先入後出記憶としてのスタツク4を形成してい
る。スタツク4は記憶装置3内のメモリアドレス
というものを特に意識せずにデータの出し入れが
できるため、副プログラム分岐の際の主プログラ
ムへの戻り番地の格納および副プログラムから主
プログラムへの復帰時の戻り番地の取り出し、演
算処理装置1内の各種レジスタの内容の退避およ
び復帰、プログラム間のデータの受け渡しなどに
頻繁に使用されている。演算処理装置1がスタツ
クポインタ2の管理の下で記憶装置3との間で母
線5を介してデータの読み書きを行なうために、
母線5の分布容量によるデータの遅延、演算処理
装置1と母線5、記憶装置3と母線5を結合する
ために用いられる母線5との送受信部ならびに送
受信制御部内でのデータの遅延が生じ、データを
正しく伝えるのに多くの時間を必要としていた。
A conventional example is shown in FIG. A stack pointer 2 is provided in the arithmetic processing unit 1, and a mechanism is formed that allows reading and writing only to the memory in the storage device 3 corresponding to the address indicated by the contents of the stack pointer 2. The stack 4 as a first-in, last-out memory is formed by increasing or decreasing the contents of the stack pointer 2 by, for example, 1 by the address area occupied by one word each time a read or write is performed. Since data can be input and output from the stack 4 without being particularly aware of the memory address in the storage device 3, it is possible to store the return address to the main program at the time of subprogram branching and to store the return address from the subprogram to the main program. It is frequently used for retrieving return addresses, saving and restoring the contents of various registers in the arithmetic processing unit 1, and passing data between programs. In order for the arithmetic processing unit 1 to read and write data to and from the storage device 3 via the bus 5 under the control of the stack pointer 2,
Data delays occur due to the distributed capacity of the bus 5, and data delays occur within the transmission/reception unit and transmission/reception control unit used to connect the processing unit 1 and the bus 5, the storage device 3 and the bus 5, and the transmission/reception control unit. It took a lot of time to convey the message correctly.

本発明は従来のかかる欠点を改善した新規なス
タツクの形成方法を提供するもので、演算処理装
置内に主(内部)スタツクを設け、これにより、
母線を介して補助(外部)スタツクとして使用さ
れる記憶装置への読み書きの頻度を下げ、データ
の受け渡しの無駄時間を軽減し、高速化を図ろう
とするものである。
The present invention provides a novel method for forming a stack that improves the conventional drawbacks, and includes providing a main (internal) stack within an arithmetic processing unit, thereby achieving the following:
This aims to reduce the frequency of reading and writing to a storage device used as an auxiliary (external) stack via the bus, reduce wasted time in data transfer, and increase speed.

以下本発明の一実施例を図面に基づいて説明す
る。第2図において、演算処理装置6は外部退避
ポインタ7、内部スタツクポインタ8、内部スタ
ツク9とこれらを結合する内部母線10を内蔵
し、外部退避領域12を内蔵する記憶装置11と
母線13を介して結合されている。外部退避ポイ
ンタ7は外部退避領域12の空の先頭位置を示
し、内部スタツクポインタ8は内部スタツク9の
空の先頭位置を示し、演算処理装置6がスタツク
への書き込み読み出し動作を行なう場合、データ
を内部スタツクポインタ8を通して内部スタツク
9に対して書き込み読み出すとともに内部スタツ
クポインタ8を更新する。また、内部スタツクが
充満状態時に演算処理装置6がスタツクへ書き込
む時は内部スタツク9の内容の一部を内部スタツ
クポインタ8、外部退避ポインタ7の値をもとに
外部退避領域12へ転送した後、内部スタツク9
に書き込むとともに内部スタツクポインタ8と外
部退避ポインタ7を更新する。また内部スタツク
9が空状態時にスタツクから読み出す時は外部退
避領域12の内容の一部を外部退避ポインタ7、
内部スタツクポインタ8の値をもとに内部スタツ
ク9へ転送した後、内部スタツク9から読み出す
とともに、内部スタツクポインタ8と外部退避ポ
インタ7を更新する。
An embodiment of the present invention will be described below based on the drawings. In FIG. 2, an arithmetic processing device 6 includes an external save pointer 7, an internal stack pointer 8, an internal stack 9, and an internal bus 10 that connects these, and a storage device 11 that includes an external save area 12 and a bus 13. are connected via. The external save pointer 7 indicates the empty start position of the external save area 12, and the internal stack pointer 8 indicates the empty start position of the internal stack 9. is written to and read from the internal stack 9 through the internal stack pointer 8, and the internal stack pointer 8 is updated. Furthermore, when the arithmetic processing unit 6 writes to the stack when the internal stack is full, part of the contents of the internal stack 9 is transferred to the external save area 12 based on the values of the internal stack pointer 8 and the external save pointer 7. After, internal stack 9
At the same time, the internal stack pointer 8 and external save pointer 7 are updated. Also, when reading from the stack when the internal stack 9 is empty, a part of the contents of the external save area 12 is transferred to the external save pointer 7,
After transferring to the internal stack 9 based on the value of the internal stack pointer 8, it is read from the internal stack 9, and the internal stack pointer 8 and external save pointer 7 are updated.

いま、内部スタツク9の容量が2n語の場合を
考え、更に詳しく説明する。プログラム実行中に
スタツク使用要求が生じた場合は内部スタツク9
に対して内部スタツクポインタ8の管理の下でデ
ータの受け渡しをする。内部スタツク9はレジス
タ配列の形成をとるように構成され、内部母線1
0を通じてデータの受け渡しをするので、演算処
理装置6内でのレジスタ間のデータの受け渡しと
同様に高速で行なうことができる。内部スタツク
9に格納されているデータが0語である時に読み
出し要求が生じた時は、外部退避ポインタ7の示
す位置からn語を記憶装置11内に形成される外
部退避領域12から母線13を介して内部スタツ
ク9の内部スタツクポインタ8の示す位置に格納
し、外部退避ポインタ7の示す位置をnだけ減
じ、内部スタツクポインタ8の示す位置をnだけ
増す。そののち、内部スタツク9に対して読み出
しを行なう。同様に、内部スタツク9に格納され
ているデータが2n語である時に書き込み要求が
生じた時は、外部退避ポインタ7の示す位置に内
部スタツク9から母線13を介して外部退避領域
12へn語格納し、外部退避ポインタ7の示す位
置をnだけ増し、内部スタツクポインタ8の示す
位置をnだけ減じる。そののち内部スタツク9に
対して書き込みを行なう。このように内部スタツ
ク9と外部スタツク12間の1回の転送語数を
2nとせずにnにすることによつて、内部スタツ
ク9の格納語数が0また2n付近での稼動頻度を
下げ、内部スタツク9と外部退避領域12間のデ
ータ転送回数を低減し、内部スタツク9内のみで
データの受け渡しができやすいようにする。
Let us now consider the case where the capacity of the internal stack 9 is 2n words and explain in more detail. If a stack usage request occurs during program execution, the internal stack 9
Data is transferred to and from the memory under the control of the internal stack pointer 8. The internal stack 9 is configured to form a register array, and the internal bus 1
Since data is transferred through 0, it can be performed at high speed similar to data transfer between registers within the arithmetic processing unit 6. When a read request occurs when the data stored in the internal stack 9 is 0 words, n words are transferred from the external save area 12 formed in the storage device 11 to the bus bar 13 from the position indicated by the external save pointer 7. The data is stored in the position indicated by the internal stack pointer 8 of the internal stack 9, the position indicated by the external save pointer 7 is subtracted by n, and the position indicated by the internal stack pointer 8 is incremented by n. Thereafter, the internal stack 9 is read. Similarly, when a write request occurs when the data stored in the internal stack 9 is 2n words, n words are written from the internal stack 9 to the external save area 12 via the bus 13 at the position indicated by the external save pointer 7. The position indicated by the external save pointer 7 is incremented by n, and the position indicated by the internal stack pointer 8 is decreased by n. Thereafter, writing is performed to the internal stack 9. In this way, the number of words transferred at one time between the internal stack 9 and the external stack 12 is
By setting it to n instead of 2n, the operation frequency when the number of words stored in the internal stack 9 is 0 or around 2n is reduced, the number of data transfers between the internal stack 9 and the external save area 12 is reduced, and the number of words stored in the internal stack 9 is reduced. Make it easy to exchange data only within the network.

一般的にいうと、内部スタツク9が(i+j+
k)語(但しi、kは正の整数、jは整数)で構
成されている場合、内部スタツク9が充満状態時
にスタツクに書き込む時は内部スタツク9の内容
のうち1語を外部退避領域12へ転送し、また内
部スタツク9が空状態時にスタツクから読み出す
時は外部退避領域12からk語を内部スタツク9
に転送する。前述実施例ではi=k=n、j=0
の場合を考えたが、i、j、kの値の組み合せは
この限りではない。
Generally speaking, the internal stack 9 is (i+j+
k) words (where i, k are positive integers, and j is an integer), when writing to the stack when the internal stack 9 is full, one word from the contents of the internal stack 9 is saved to the external save area 12. When reading from the stack when the internal stack 9 is empty, the k word is transferred from the external save area 12 to the internal stack 9.
Transfer to. In the above embodiment, i=k=n, j=0
We have considered the case of , but the combination of values of i, j, and k is not limited to this.

以上説明したように本発明のスタツク形成方法
は、スタツク操作は記憶装置を対象に行なわれる
のではなく、内部スタツクとして演算処理装置内
に設けられたスタツク用レジスタ配列を対象に行
なわれる。内部スタツクの容量を越える範囲の語
数を扱う場合にも、容量を越えるスタツクの底部
の情報を外部退避領域に一時的に退避することに
より、やはり、スタツク操作は内部スタツクに対
してのみ行なわれる。したがつて、スタツクの深
さ及び内部スタツクの容量に依存せずに、常に内
部スタツクを用いた高速なスタツク操作が行なわ
れ、その実用的効果は大きい。
As explained above, in the stack forming method of the present invention, the stack operation is not performed on the storage device, but on the stack register array provided in the arithmetic processing unit as an internal stack. Even when handling a number of words that exceeds the capacity of the internal stack, stack operations are still performed only on the internal stack by temporarily saving information at the bottom of the stack that exceeds the capacity to the external save area. Therefore, high-speed stack operation using the internal stack is always performed regardless of the depth of the stack and the capacity of the internal stack, and its practical effects are great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のスタツク形成方法を示すブロツ
ク図、第2図は本発明によるスタツク形成方法を
示すブロツク図である。 6……演算処理装置、7……外部退避ポイン
タ、8……内部スタツクポインタ、9……内部ス
タツク、10……内部母線、11……記憶装置、
12……外部退避領域、13……母線。
FIG. 1 is a block diagram showing a conventional stack forming method, and FIG. 2 is a block diagram showing a stack forming method according to the present invention. 6... Arithmetic processing unit, 7... External save pointer, 8... Internal stack pointer, 9... Internal stack, 10... Internal bus, 11... Storage device,
12... External evacuation area, 13... Bus bar.

Claims (1)

【特許請求の範囲】 1 演算処理装置、それが実行すべきプログラム
および取扱うデータを格納する記憶装置、それら
を結合する母線から成る情報処理装置を用いて、
プログラム内でのデータの受け渡しに先入後出の
スタツクを形成するにあたり、前記記憶装置内に
外部退避領域、前記演算処理装置内に内部スタツ
クおよび該内部スタツクの空の先頭位置を示す内
部スタツクポインタ、該外部退避領域の空の先頭
位置を示す外部退避ポインタを有し、前記演算処
理装置がスタツクへの書き込み読み出し動作を行
なう場合、データを前記内部スタツクに対して書
き込み読み出すとともに前記内部スタツクポイン
タを更新し、前記内部スタツクが充満状態時にス
タツクに書き込む時は前記内部スタツクの内容を
前記外部退避領域へ転送し充満状態を解消した後
前記内部スタツクに書き込むとともに前記内部ス
タツクポインタ、前記外部退避ポインタを更新
し、前記内部スタツクが空状態時にスタツクから
読み出す時は前記外部退避領域の内容を前記内部
スタツクへ転送し、空状態を解消した後前記内部
スタツクから読み出すとともに前記内部スタツク
ポインタ、前記外部退避ポインタを更新する機能
を有することを特徴とするスタツク形成方法。 2 内部スタツクが(i+j+k)語(ただし
i、kは正の整数、jは整数)で構成され、内部
スタツクが充満状態時にスタツクに書き込む時は
内部スタツクの内容のうち下位の(最も古い)i
語を外部退避領域の上位(先頭)へ転送し、また
内部スタツクが空状態時にスタツクから読み出す
時は外部退避領域から上位(最も新しい)k語を
内部スタツクの上位(先頭)に転送することを特
徴とする特許請求の範囲第1項記載のスタツク形
成方法。
[Claims] 1. Using an information processing device consisting of an arithmetic processing device, a storage device that stores programs to be executed and data handled by the arithmetic processing device, and a bus that connects them,
When forming a first-in, last-out stack for data exchange within a program, an external save area is provided in the storage device, an internal stack is provided in the arithmetic processing unit, and an internal stack pointer indicates the empty head position of the internal stack. , has an external save pointer indicating the empty head position of the external save area, and when the arithmetic processing unit performs a write/read operation to/from the stack, it writes/reads data to/from the internal stack and also points to the internal stack pointer. When writing to the stack when the internal stack is full, the contents of the internal stack are transferred to the external save area, and after the full state is cleared, the contents are written to the internal stack, and the internal stack pointer and the external save area are updated. When updating the pointer and reading from the stack when the internal stack is empty, the contents of the external save area are transferred to the internal stack, and after the empty status is resolved, reading from the internal stack is performed, and the internal stack pointer and the A stack forming method characterized by having a function of updating an external save pointer. 2 When the internal stack is composed of (i+j+k) words (where i, k are positive integers, and j is an integer), and the internal stack is full, the lower (oldest) i of the contents of the internal stack is written.
This function transfers the word to the top (top) of the external save area, and when reading from the stack when the internal stack is empty, transfers the top (newest) k words from the external save area to the top (top) of the internal stack. A method of forming a stack according to claim 1.
JP56203269A 1981-12-15 1981-12-15 Stack forming method Granted JPS58103043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56203269A JPS58103043A (en) 1981-12-15 1981-12-15 Stack forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56203269A JPS58103043A (en) 1981-12-15 1981-12-15 Stack forming method

Publications (2)

Publication Number Publication Date
JPS58103043A JPS58103043A (en) 1983-06-18
JPS6149696B2 true JPS6149696B2 (en) 1986-10-30

Family

ID=16471240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56203269A Granted JPS58103043A (en) 1981-12-15 1981-12-15 Stack forming method

Country Status (1)

Country Link
JP (1) JPS58103043A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242800A (en) * 1985-02-19 1986-10-29 ビーペックス・コーポレーション Die segment for rotary die and rotary die device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01255035A (en) * 1988-04-05 1989-10-11 Matsushita Electric Ind Co Ltd Processor
JPH02299025A (en) * 1989-05-12 1990-12-11 Nec Corp Microcomputer
US20070282928A1 (en) * 2006-06-06 2007-12-06 Guofang Jiao Processor core stack extension

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5241132A (en) * 1975-09-29 1977-03-30 Hitachi Ltd Molten plating method
JPS54146531A (en) * 1978-05-09 1979-11-15 Fujitsu Ltd Address stack control system
JPS5730167A (en) * 1980-07-30 1982-02-18 Fujitsu Ltd Stack memory device
JPS5730166A (en) * 1980-07-30 1982-02-18 Fujitsu Ltd Stack memory processor
JPS6012658B2 (en) * 1980-12-22 1985-04-02 富士通株式会社 stack memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242800A (en) * 1985-02-19 1986-10-29 ビーペックス・コーポレーション Die segment for rotary die and rotary die device

Also Published As

Publication number Publication date
JPS58103043A (en) 1983-06-18

Similar Documents

Publication Publication Date Title
JP3598321B2 (en) Buffering data exchanged between buses operating at different frequencies
US4742446A (en) Computer system using cache buffer storage unit and independent storage buffer device for store through operation
JPS6149696B2 (en)
EP0787326B1 (en) System and method for processing of memory data and communication system comprising such system
JPH0383134A (en) Stack management method
JPS63233435A (en) Delay processing method and device
JPS6198469A (en) Inter-microprocessor communications system
JP2734581B2 (en) Control method of input / output control unit
JPH05233440A (en) Data transfer system equipped with buffer function
JP3057754B2 (en) Memory circuit and distributed processing system
JP2687679B2 (en) Program development equipment
JP2581144B2 (en) Bus control device
JPH06139201A (en) Information transfer method via shared memory
JPH03149626A (en) Method for controlling stack
JPS5533282A (en) Buffer control system
JPS6218074B2 (en)
JPH04333950A (en) Information processing system
JPS616747A (en) Memory device
JPH0115100B2 (en)
JPS58215778A (en) Buffer storage control system
JPS6243737A (en) Interrupt control method
JPS6375927A (en) Buffer control method
JPS61153770A (en) Image processor
JPH04127227A (en) memory control system
JPS6215651A (en) Information processing system