JPS6150357B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and particularly to service request control when the same service processing device is shared by a plurality of service requesting devices.

As an example of a configuration in which multiple service request devices share the same service processing device, there is a central processing unit (service request device) with a multiprocessor configuration, a memory control device, and a memory device (service processing device).
However, in this type of configuration, it is necessary to control service requests so that there is no conflict between service request devices.

FIG. 1 is a diagram for explaining a general memory control device when two central processing units (CPUs) share one memory. Here, two
If we temporarily name the CPUs CPU0 and CPU1, 1 is
This memory is shared by CPU0 and CPU1, and the memory control device is composed of a memory control unit 13 for CPU0 and a memory control unit 14 for CPU1. 2 is the signal EX0 that requests service from CPU 0 to memory 1, and 3 is the CPU
Service request signals EX1 and 4 from 1 are signals BANK BUSY0 indicating that memory 1 is currently being used by CPU0, and 5 is a signal BANK BUSY1 from CPU1. 6 is BANK
This is a 0-side latch that holds the BUSY0 signal 4, and is set by the EX0 signal 2. Similarly 7
is a 1-side latch that holds the BANK BUSY1 signal, and is set by the EX1 signal 3. 8 is a signal ADV0 for notifying CPU0 that the read/write operation in memory 1 has been completed;
Used to reset the 0 side latch 6. Similarly, 9 is a signal ADV1 that notifies the CPU 1 of the completion of read and write operations in the memory 1, and is used to reset the latch 7 on the first side. 10 is
Captures various memory requests from the REQ terminal,
This is a 0-side priority control circuit that determines priority depending on the type of memory request and generates EX0 signal 2. Similarly, 11 is a 1-side priority control circuit that generates EX1 signal 3. When the priority control circuits 10 and 11 have an input to their INH terminals, the EX0 signal 2 or
EX1 signal 3 is not generated. In Figure 1, BANK BUSY0 signal 4 and BANK BUSY1 signal 5 are sent to each priority control circuit 1 through an OR circuit.
0 and 11, so if these signals are “1”, EX0 signal 2 or EX1 signal 3
deter. 12 is “0” and “1” at regular intervals
This CPU cycle signal is input to the priority control circuits 10 and 11 through an OR circuit, respectively, so that EX0 signal 2 is generated when it is "0" and EX1 signal 3 is generated when it is "1". ing.

Next, the operation of the memory control unit shown in FIG. 1 will be explained with reference to FIG. In Figure 2, CPU
Assume that a memory request occurs in CPU 0 and CPU 1 at the same time, but because the CPU cycle is “0”, EX0 signal 2 occurs. This signal starts the memory operation and also sets the 0 side latch 6.
BANK BUSY0 signal 4 is set to “1”, and currently the CPU
0 indicates that memory 1 is in use, and prevents the EX0 signal 2 or EX1 signal 3 from being generated again even if other memory requests from CPU0 and CPU1 occur. When the memory operation is completed, the ADV0 signal 8 is output to notify the CPU0, and at the same time, the 0 side latch 6 is reset and BANK is completed.
Set the BUSY signal 4 to “0” so that the next memory request can be taken. In Figure 2, at this time
Since the CPU cycle signal 12 is “0”, the memory request of CPU0 is selected again, and EX0
Produces signal 2. And BANK BUSY0 again
When reset with CPU cycle "0", the memory request of CPU0 is selected again.
During this time, the memory request of CPU1 is not selected no matter how long it takes.

As mentioned above, conventionally, CPU cycles and BANK
Since competition between memory requests is controlled only by the BUSY signal, depending on the relationship between the sets and resets of the two, only one memory request may be selected continuously, and the other memory request may be selected no matter how long. However, there was a problem in that the process was not processed properly. This allows one memory to be
Generally speaking, similar problems occur when the same service processing device is shared by multiple service requesting devices.

The present invention solves the above conventional problems, and provides a service processing device that can equally process requests from each service requesting device when the same service processing device is shared by multiple service requesting devices. It is about providing.

A feature of the present invention is that, for example, when the service request device is a central processing unit (CPU), and the service processing device is a memory and a memory control device, BANK
The BUSY signal is separated into one for self-memory control unit reporting and another for other memory control unit reporting.
A delay latch is installed to delay the BANK BUSY signal by one CPU cycle compared to that reported in other reports.
As a result, after the own CPU's memory request is processed, other CPU's memory requests are given priority and the memory requests of each CPU can be processed equally.

FIG. 3 is a block diagram of one embodiment of the present invention, and FIG. 4 is a diagram showing the time relationship of each signal to explain the operation of FIG. 3.

Figure 3, similar to Figure 1, is an example where two CPUs share one memory.
If we temporarily name the CPUs CPU0 and CPU1, 1 is
Memory shared by CPU0, CPU1, 2
1 is the memory control unit for CPU0, 22 is the CPU
1 memory control unit. 2 is EX0 signal,
3 is the FX1 signal, 8 is the ADV0 signal, 9 is the ADV1 signal, 18 is the 0 side priority control circuit, 19 is the 1 side priority control circuit, and 20 is the CPU cycle signal, which have the same function as explained in Figure 1. do. 4 is
BANK BUSY0 signal, currently for CPU1
Notifies that memory 1 is being used by CPU0. At the same time, 5 is the BANK BUSYA1 signal, which informs CPU0 that memory 1 is currently being used by CPU1. 6 is BANK
BANK to hold BUSYA0 signal 4
BUSYA0 latch, set by EX0 signal 2. Similarly, 7 is BANK BUSYA1 signal 5
BANK BUSYA1 latch that holds EX1
Set by signal 3. 10 is BANK
BUSYB0 latch, set by EX0 signal 2. Similarly, 11 is a BANK BUSYB1 latch, which is set by EX1 signal 3. 12
is the BANK BUSYB0 signal, which indicates to the own CPU that memory 1 is currently being used by CPU 0.
This is a signal to notify (CPU0).
Similarly, 13 is the BANK BUSYB1 signal, and other
This is a signal to notify the CPU (CPU1). BANK BUSYB0 signal 12, BANK
BUSYB1 signal 13 is passed through an OR circuit,
0 side priority control circuit 18, 1 side priority control circuit 19
Connected to INH terminal. 14 and 15 are delay latches (hereinafter referred to as D latches), and ADV0
BANK by delaying signal 8 by 1 CPU cycle
This is input to the R terminal of the BUSYB0 latch 10 to reset it. Similarly, 16 and 17 are D latches, which delay the ADV1 signal 9 by one CPU cycle and reset the BANK BUSYB1 latch 11.

Next, the operation shown in FIG. 3 will be explained with reference to FIG. Assume that, as in the case of FIG. 2, memory requests for CPU0 and CPU1 occur simultaneously, but since the CPU cycle is "0", the memory request for CPU0 is selected and EX0 signal 2 is generated. This signal causes BANK BUSYA0 latch 6
, BANK BUSYB0 latch 10 is set,
BANK BUSYA0 signal 4 is the INH terminal 12 of the 1st side priority control circuit 19, BANK BUSYB0 signal 1, respectively.
2 is input to the INH terminal of the 0 side priority control circuit 18 through the OR circuit, and the subsequent EX0 signal 2 and EX1
Suppress signal 3. When the operation in memory 1 is completed, the ADV0 signal 8 is generated and resets the BANK BUSYA0 latch 6.
Since signal 8 is input, BANK BUSYB0 signal 12 is reset one CPU cycle later than BANK BUSYA0 signal 4. As shown in Figure 4, when the BANK BUSYA0 signal 4 is reset, the CPU cycle is "0", so the CPU1
It is not possible to accept memory requests, but because BANK BUSYB0 signal 12 is “1”,
Memory requests from CPU0 will not be accepted again. Thereafter, when the CPU cycle becomes "1", the memory request of CPU1 is accepted and Ex1 signal 3 is generated. Thereafter, the same operation is repeated to alternately accept and process memory requests from CPU0 and CPU1.

As is clear from the above explanation, according to the present invention, the BANK BUSY signal is used for reporting by the own CPU and for other CPUs.
By separating it for CPU reporting and shifting it by one CPU cycle, after the own CPU's memory request is accepted, by giving priority to accepting other CPU's memory requests,
By balancing memory request processing between CPU0 and CPU1, processing can be performed smoothly even if the memory is shared between two CPUs.

The above is a case where one memory is shared by two CPUs, but it goes without saying that the present invention is applicable to other configurations as well.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a conventional service processing device, FIG. 2 is a timing diagram for explaining the operation of FIG. 1, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram for explaining the operation of FIG. 3. FIG. 1... Memory, 6, 7, 10, 11... Latch, 14, 15, 16, 17... Delay latch, 18, 19... Priority control circuit, 21, 22...
...Memory control unit.

Claims (1)

[Claims] 1. In a data processing device in which the same service processing device is shared by a plurality of service requesting devices, priority control means receives various service requests, determines priorities, and generates a service operation start signal when no suppression condition is input. means for holding a signal set by the service operation start signal and reset by the service operation end signal for suppressing the service operation start signal of another service requesting device; means for delaying the service operation by a certain period of time; and means for holding a signal for using the signal delayed for a certain period of time as a reset signal, using the service operation start signal as a set signal, and suppressing the service operation start signal of the own service requesting device. A data processing device comprising: