JPS6153855B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to field effect integrated circuit semiconductor devices, and more particularly to field effect integrated circuit semiconductor devices having check transistors.

Generally, an integrated circuit semiconductor device requires several photo-etching processes to complete it, and it is impossible to completely eliminate deviations between the respective etching processes. The main reasons for this are manufacturing variations in the etching mask and mechanical deviations caused by the photolithography exposure machine.

Conventionally, photo-etching masks have been designed taking the above-mentioned deviations into account, but recently, with the improvement in the degree of integration (number of elements per unit area), the margin between photo-etching processes has become smaller, and if some If the misalignment occurs due to a cause and the misalignment has a serious effect on the electrical characteristics of the integrated circuit semiconductor device, it is necessary to remove the product at an early stage, and if the abnormality cannot be visually confirmed, the product must be removed. Even if a product fails in an electrical test after completion, it is necessary to quickly identify the cause.

In an insulated gate field effect transistor,
By implanting high-concentration impurity ions of the same conductivity type as the drain near the interface with the channel on the surface of the drain diffusion region, electric field concentration near the drain diffusion region on the surface of the semiconductor substrate under the gate insulating film is alleviated, and the drain breakdown voltage is increased. There are ways to improve.

FIG. 1 is a cross-sectional view of an example of a conventional insulated gate field effect transistor.

In the figure, 1 is a semiconductor substrate, 2 is a source diffusion region, 3 is a drain diffusion region, 4 is a gate insulating film,
5 is a gate electrode, 6 and 6' are source and drain electrodes, and 7 is an impurity ion implantation region, which is provided to improve the above-mentioned drain breakdown voltage. In this case, if the drain diffusion region 3 and the impurity ion implantation region 7 are significantly misaligned, it is impossible to improve the drain breakdown voltage. Moreover, the deviation in this case cannot be visually confirmed. Furthermore, since the insulated gate field effect transistor having the above structure may be arranged in any direction on the semiconductor device, misalignment may occur in many directions.

The present invention provides a field effect integrated circuit semiconductor device having a check transistor capable of detecting abnormalities in the semiconductor device.

A feature of the present invention is that the current flows between the drain and the source in four orthogonal directions, and the check field effect transistor is designed so that the current flows equally in each direction on the same substrate as the internal elements. In field effect integrated circuit semiconductor devices.

The present invention will be explained by examples.

FIG. 2 is a plan view (figure a) of a check field effect transistor according to the first embodiment of the present invention, and a cross-sectional view taken along line A-A' in figure a (figure b).

A source diffusion region 22 and a drain diffusion region 23 of a conductivity type opposite to that of the substrate are provided in a semiconductor substrate 21 of one conductivity type, and an ion implantation region 24 for improving drain breakdown voltage is further provided. As shown in the figure, the drain diffusion region 23 surrounds the source diffusion region 22 once, and is formed so that the source-drain current flows evenly in the four directions of the X-Y axis.
The back surface of the substrate is covered with a gate insulating film 25 and a field insulating film 26, and a source contact 27,
Drain contact 28, 28', 28'', 28
is provided. The gate electrode and the source electrode are connected to form a source/gate electrode 29, and the drain electrode 30 is formed so that current flows equally in four directions through the four drain contacts 28, 28', 28'', and 28. be done.

A check field effect transistor with the above structure is formed in the substrate at the same time as the original internal elements,
The source and gate electrodes 29 of this check transistor are set to the substrate potential, and a voltage is variably applied to the drain electrode 30 to measure the drain breakdown voltage to determine whether a target breakdown voltage value is obtained. If the desired breakdown voltage value cannot be obtained, it means that there is a shift in the ion implantation region 24, and a defective wafer can be detected at an early stage.

In the manufacturing of field-effect semiconductor devices, not only the positional deviation of the ion implantation region as described above, but also
There is also a misalignment of the polycrystalline silicon gate electrode. If it is desired to detect such a deviation, it is necessary to form a check transistor suitable for the detection.

FIG. 3 is a plan view (figure a) and a sectional view taken along line B-B' of figure a (figure b) of a check field effect transistor according to a second embodiment of the present invention.

A field insulating film 32 is provided on a semiconductor substrate 31, an opening is formed in an element formation region, and a gate insulating film 33 is provided in the opening. After a polycrystalline silicon layer is provided on the insulating films 32 and 33, patterning is performed to form a polycrystalline silicon gate electrode 34 extending in four right-angled directions. Thereafter, by performing diffusion through the gate insulating film 33, the source and drain diffusion regions 35 and 36 are formed in a checkered pattern as shown in figure a, and by oxidation, the entire surface is covered with the insulating film 3.
Cover with 7. Source and drain contact hole 3
8 and 39 are opened, and at the same time, the insulating film 37 at the contact portion with the polycrystalline silicon gate is removed to form a gate contact hole 40. A drain electrode 41 and a source/gate electrode 42 in which the source and gate are connected are formed by wiring metal such as Al. The tip of the silicon gate electrode 34 protrudes from the outer periphery of the source and drain diffusion regions 35 and 36 by a predetermined width W. As described above, since the source, drain, and gate are arranged evenly in the four directions, the source-drain current flows equally in the four directions.

A check field effect transistor with the above structure is formed in the substrate at the same time as the original internal elements,
The source/gate electrode 42 is brought to the substrate potential, a voltage is applied to the drain electrode 39, and the current is examined. Since the source and drain diffusion regions of this check transistor are formed in a self-aligned manner, if the polycrystalline silicon gate electrode 36 does not protrude from the source and drain diffusion regions 32 and 33, the source and drain diffusion regions Since these are short-circuited and a large current flows, any misalignment of the polycrystalline silicon gate electrode can be immediately detected.

As explained above, by forming the check transistor of the present invention in the substrate at the same time as the original internal elements and electrically checking this, defects due to misalignment in multiple directions can be immediately detected, thereby facilitating semiconductor device manufacturing. The effect is remarkable.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an example of a conventional insulated gate field effect transistor, and FIG. 2 is a plan view (a) of a check field effect transistor according to a first embodiment of the present invention. Figure 3 is a plan view (Figure a) of a check field effect transistor according to a second embodiment of the present invention, and a cross-sectional view taken along line B-B' in Figure A (Figure B). 1... Semiconductor substrate, 2... Source diffusion region, 3
...Drain diffusion region, 4...Gate insulating film, 5
...gate electrode, 6...source electrode, 6'...drain electrode, 7...impurity ion implantation region, 21
... Semiconductor substrate, 22 ... Source diffusion region, 23
...Drain diffusion region, 24...Ion implantation region, 25...Gate insulating film, 26...Field insulating film, 27...Source contact, 28,2
8', 28'', 28...Drain contact, 2
9... Source/gate electrode, 30... Drain electrode, 31... Semiconductor substrate, 32... Field insulating film, 33... Gate insulating film, 34... Polycrystalline silicon gate electrode, 35... Source diffusion region, 3
6...Drain diffusion region, 37...Insulating film, 38
...Source contact hole, 39...Drain contact hole, 40...Gate contact hole, 41...
...Drain electrode, 42...Source/gate electrode.

Claims (1)

[Claims] 1. It is characterized by having a check field effect transistor on the same substrate as internal elements, which is designed so that the current flows between the drain and the source in four orthogonal directions, and the current flows equally in each direction. Field-effect integrated circuit semiconductor device.