JPS6155066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wire bundle testing device that uses a small number of gate circuits and is capable of determining wiring connection errors and the like in a wire bundle in a short time.

When a large number of electrical conductors are bundled together to connect devices or circuits within a device, the bundled electrical conductors are manufactured in advance and tested to ensure continuity of each conductor and connection with other wires as designed. It is required to use the following. Various tests for such wire bundles have been proposed in the past. Although manual testing using a tester or buzzer is simple and easy to handle, it is naturally inefficient. In order to improve efficiency, tests have been conducted using a computer and the results printed out using a printer, but this method is complicated and expensive to handle.

Therefore, in order to eliminate the above-mentioned drawbacks, a wire bundle testing device centered on a gate circuit was proposed, and its block diagram is shown in FIG. In FIG. 1, each test terminal of a circuit under test 1 is connected to each terminal of an interface circuit 2, so that the circuit under test 1 can be replaced and connected in sequence. Among the terminals of the circuit under test 1, those to be connected to the same potential are grouped into one system, and each system is connected to gate circuits 3-1 to 3-n, respectively. One interface circuit 2 may be provided for each type of circuit under test 1. One output is taken out from each gate circuit 3 and guided to a holding circuit 4. The outputs of the holding circuits 4-1 to 4-n are connected to indicator lamps 5-1 to 5-n, respectively. In addition, from the pulse generation circuit 6 to each gate circuit 3-
Outputs are coupled to terminals 1 to 3-n. The signals from this pulse generation circuit 6 are transmitted to gate circuits 3 and 3 respectively.
It is connected to each line of each system led from the interface circuit 2 inside. First, one pulse is sent from the pulse generation circuit 6 to the first gate circuit 3-1. This is sent out to one line of the first system, but if the wiring is normal in the circuit under test 1, a pulse will appear on all the lines of the first system, and the first No pulse should appear on any line of the system other than the system. This is checked by each gate circuit at the same time as the pulse is sent. If a pulse does not appear on any of the lines connected to the first gate circuit 3-1, the first gate circuit 3-1 outputs a signal, which is held in the holding circuit 4-1. The display lamp 5-1 is lit continuously. This means that there is a disconnection in the first system of the circuit under test. At this time, if a pulse appears on the line connected to the third gate 3-3, the lamp 5-3 will light up as well, indicating a short circuit between the first and third systems. . In this way, pulses are sent out sequentially from the pulse generating circuit 6 to test all systems. If the pulse generating circuit 6 is configured to automatically sequentially generate pulses by pressing the start button, the test result will be good if no indicator lamp 4 lights up until the sequential pulses are completed. However, in the conventional device described above, the interface circuit 2
This is done by connecting systems that should be connected to the same potential in a closed loop, or by giving a signal to one terminal that has the same potential and calculating the AND of all other terminal outputs, but the former The method described above cannot accurately detect the wiring number of a disconnected wire, and the latter method requires complicated wiring within the interface.

The purpose of the present invention is to improve the above-mentioned drawbacks by using a master wire bundle that has been confirmed to be properly connected in advance, and by comparing it with the master wire bundle, it is possible to eliminate mistakes in wiring connections in a short time with a simple configuration. It is an object of the present invention to provide a wire bundle testing device that can determine the wire number of a defective conductor wire and can also accurately detect the wire number of a defective conductor wire.

Embodiments of the present invention shown in the drawings will be described below. FIG. 2 shows a circuit configuration diagram of the first embodiment of the present invention, and for the sake of clarity, only the apparatus for testing four wire bundles is shown. M1 to M4 indicate terminals to which one end of the master wire bundle is to be connected, and m1 to m4 indicate terminals to which one end of the wire bundle to be tested is connected. s1 to s4 are application terminals for sequential timing pulses, that is, pulses that are generated sequentially in time; EX1;
EX4 to EX4 are exclusive OR gates NAND1 to
NAND8 is NAND gate, B1 to B4, B1
1, B12 is a buffer amplifier, D1 to D8, D
11 to D18 are diodes (unidirectional elements),
AND1 to AND3 are AND gates B11, B
The circuit output signal of the NAND gate is applied to the determination circuit via the unidirectional element. "Unwired"
For "excess wiring" and "miswiring", an output appears when there is a defective wiring, for example, to light up a display element.

In this specification, "unwired" refers to a defect in which terminals that should originally be connected are not connected to each other.
Excess wiring is a defect in which terminals that are not originally connected are electrically connected to each other, and incorrect wiring is a defect in which a certain terminal is not connected to the terminal it should be connected to, but is connected to another terminal. In other words, this refers to a case where unwired lines and surplus lines occur at the same time.

When operating the wire bundle testing device shown in Fig. 2, connect the predetermined terminal of the master wire bundle to the M terminal, connect the corresponding terminal of the wire bundle to be tested to the m terminal, and connect the terminal S
Press the start button to apply a pulse or generate a repetitive sweep. Repeated sweep generation is effective when a workbench is connected to a test device and a defective part is checked while being corrected.

(1) First, if there is no defect in the m terminal, when a positive pulse is applied to S1, EX1A,
EX1B is both “H”, therefore EX1F is “L”, NAND1B and NAND2A are “L”,
NAND because NAND1A and NAND2B are “H”
1F and NAND2F are both "H", and they are both blocked by D11 and D12, and B11,
Does not reach B12. At this time, since no pulse is applied to S2, both EX2A and EX2B are "L", and EX2F is "L".NAND3A, 3B,
Because NAND4A and 4B are all “L”,
Both NAND3F and NAND4F become "H".
This was also blocked by D13 and D14, and B11 and B1
Does not reach 2. In this way, diode D
All output signals are blocked by signals 11 to D14 and do not reach B11 and B12, so the signal state of the output "L" is not changed for any of the "unwired", "excess wired" and "erroneous wired" terminals. Also S1
Even if pulses are sequentially applied to any other terminals other than B11 and B12, the outputs of B11 and B12 will still remain at "L".

(2) Next, if an unwired defect occurs.For example, as shown in Figure 3, even though M1-M2 are connected, if m1-m2 is unwired, S1 is applied. When, M1-
EX2A is “H” through the connection line of M2. Since no pulse is input to S2, EX2B is “L”, therefore EX2F is “H”, NAND3
Both A and 3B are "H", and NAND3F is "L", so the output "L" signal of B11 changes to "H" via D13, and as a result of the operation by AND1, an "H" signal is sent to the "unwired" terminal. It can be seen that there is an unwired defect related to the pulse terminal S1, that is, the terminal m1. If a light emitting diode and an alarm generator are attached to the "unwired" terminal, defects can be detected immediately and by an alarm sound.

Since NAND4A is "H" and NAND4B is "L", NAND4F becomes "H" and the signal of B12 does not change.

Next, when the pulse of S1 ends and a pulse is applied to S2, the NAND1
F becomes "L" and an "H" signal is obtained at the "unwired" terminal. It can be seen that there is an unwired defect related to the pulse terminal S2, that is, the terminal m2. As a result, in addition to the defective location in the case of S1 mentioned above, terminal m1
- m2 can be found to be an unwired defect.

(3) Regarding the case of faulty wiring For example, as shown in Figure 4, if M1 and M2 are connected, but m1 and m2 are not connected and m1 and m3 are connected, the connection goes to S1. EX2A “H”, EX2B “L” by applying the pulse of
Therefore, EX2F is "H", and both NAND3A and 3B are "H", and NAND3F is "L", so the output of B11 is "H". EX3 at the same time
EX3F “H” because A “L”, EX3B “H”
Therefore, both NAND6A and NAND6B are “H”,
Since NAND6F is "L", the output of B12 is "H". Therefore, since each output of B11 and B12 is both “H”, the “miswiring” terminal is “H”.
(The "unwired" and "redundant wire" terminals remain at "L"). Therefore, it can be seen that there is a wiring error related to S1, that is, terminal m1.

Next, when S2 is applied, NAND1F becomes "L" and becomes "unwired" in relation to S2, that is, terminal m2.
A defect is displayed.

Then, when S3 is applied, NAND2F goes “L”
Thus, an "excess wiring" defect is displayed in relation to S3, that is, terminal m3.

Therefore, it can be determined that the wiring that should be connected from m1 to m2 is incorrectly wired from m1 to m3.

(4) Regarding the case of defective extra wiring For example, as shown in Figure 5, M1-M2 and M
3-M4 is connected while m1-m2
and m3-m4 are connected, and m2-m3 is also connected, by applying a pulse to S1
Both EX3B and EX4B are “H”, EX3A, EX
4A is both “L”, EX3F and EX4F are both “H”, so NAND6A, EX6B, NAND
8A and 8B are both “H”, NAND6F,
Both NAND8F become "L", and an "extra wiring" signal is generated from B12. Therefore, it can be seen that there is a defective extra wiring related to S1, that is, terminal m1. Next, when pulses are sequentially applied to the S2, S3, and S4 terminals, a signal indicating an extra wiring defect is generated in connection with the terminals m2, m3, and m4 each time.
Therefore, it is possible to detect a defect in which the terminals m1, m2, m3, and m4 are shorted to each other.

Or, as shown in the terminal connection diagram in Figure 6, there is a m3-m4 connection for the wire bundle under test.
Even when there is no connection between m1 and m2 and instead there is a connection between m1 and m3, if pulses are applied sequentially from S1 in the same way as described above, it will be determined that m1 is "miswired", m2 is "unwired", and m3 is "excess". A "wiring" signal is generated, allowing you to know if there is a defect.

(5) Regarding the number of terminals in the bundle of wires to be tested and the number of terminals in the test device. For example, when using a device with 100 terminals as the test device and testing a bundle of wires with 90 terminals, M1 to M90 are used as the terminals of the test device. Then, when the input to the pulse application terminal S90 is completed, a test end signal is issued. This can be done by simply connecting the test end signal source to the terminal S90. this is
As described in (1), if there is no defect, the test proceeds sequentially to S90, and if there is a defect midway through, a display is displayed, and it is also easy to construct a configuration in which the sending of timing pulses is stopped sequentially by a defect detection signal. This is because it can be done.

(6) Regarding the case where there is a defective wiring between unconnected terminals in the master wire bundle For example, as shown in Figure 7, M1 and M2 are originally not connected, but m1 and m2 are connected. When a pulse is applied to S1, EX1
EX1F is “L” because A is “H”, EX1B is “H”, and NAND2A is “L” because the same is 2B “H”.
NAND2F becomes “H”, while EX2A
EX2F is “H” because “L” and 2B “H”.
Because NAND4A “H”, NAND4B “H”,
NAND4F becomes “L” and m1 indicates an “excess wiring” defect via B11. Next, when a pulse is applied to S2, it operates in the same manner, and NAND2F becomes "L", and m2 indicates an "excess wiring" defect through B11. Therefore, it can be seen that there is an extra wire between m1 and m2.

When using the embodiment shown in FIG. 2 in this way, after connecting the terminals of the wire bundle to be tested and the terminals of the master wire bundle to the terminals of the test equipment, a timing pulse is applied from the S1 terminal. By applying this voltage, it is possible to immediately know whether there is any connection failure related to the first terminal m1 of the wire bundle under test. Next, if the next timing pulse is applied from the S2 terminal and the test is carried out sequentially up to the final terminal, a defect can be detected by only one sweep of the sequential timing pulses.

Next, FIG. 8 shows a circuit configuration diagram of a second embodiment of the present invention. FIG. 8 shows a device that can easily determine which wire number in a bundle of wires is defective. M1P and M1Q are the terminals to be connected to the first wire of the master wire bundle, m1
p and m1q are the terminals to be connected to the first wire of the wire bundle under test, and M2P, etc. are the same. TRB
1. TRB2 is a tri-state element. When no control pulse is applied to the control terminals T1, T2, etc., the input and output of the element is in an open state, and when the control pulse is applied, the "H" and "L" states of the input are output. It is. FF is a set-reset type flip-flop, LD is a light emitting diode, EX,
NAND is a symbol indicating a gate similar to that in FIG. Then, a combination of NANDs 11 and 12 is provided corresponding to both ends of the wire bundle, and this combination and FF and LD are provided in correspondence with wire numbers, and numbers are displayed somewhere when the wire numbers can be read directly.

Now, when a control pulse is applied to the control terminal T1, the tri-state element TRB1 of the device operates simultaneously, and timing pulses are sequentially applied from the terminal S1. The first wire is tested for unwired defects. In other words, if m1p-m1q are normal conductors, the outputs of NAND1 and NAND3 are the same,
The output of NAND11 becomes "L" and FF cannot be set. Therefore, the LD does not emit light. If there is a disconnection, a light-emitting display will be displayed. Next, a pulse is applied from S2 and tested in the same manner, followed by S3 and S4. When unwired defects are detected, after repairing them, a control pulse is applied to the control terminal T2, and timing pulses are sequentially applied again from the terminal S1 to test for remaining wiring defects.

In this way, according to the present invention, since the test is performed by comparing with the normally connected master conductor bundle, the location where the defect has occurred can be accurately determined in a short time. Just by creating a simple circuit that corresponds to the wire number,
It is possible to immediately detect the wire number of a defective conductor, which is extremely effective in practice.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional wire bundle testing device, Figure 2
The figure is a circuit configuration diagram of the first embodiment of the present invention, Figures 3 to 5 are operation explanatory diagrams of Figure 2, Figure 6 is a terminal connection diagram in case of a defective product, and Figure 7 is the diagram of Figure 2. FIG. 8 shows a circuit configuration diagram of a second embodiment of the present invention. M1, M2...M1P, M1Q...Master wire bundle connection terminal, m1, m2...m1p, m1q...Test wire bundle connection terminal, S1, S2...Sequential timing pulse application terminal, EX1, EX2...Exclusive OR gate, NAND1 , NAND2...NAND gate, AND
1, AND2...AND gate, B1, B2...B1
1, B12...Buffer amplifier, TRB1, TRB2
...tristate element.

Claims (1)

[Scope of Claims] 1. A pulse generation circuit for simultaneously and sequentially applying timing pulses to one end of a bundle of wires to be tested and one end of a normally connected master wire bundle, and the test wire bundle and the master wire. an exclusive OR operation circuit 1 provided corresponding to one end of each electric wire in the bundle and corresponding to each electric wire for detecting the connection state of each electric wire when the pulse is applied;
A set of gate circuits consisting of one gate circuit and two AND operation circuits, each of the gate circuit output signals of the set is applied via a unidirectional element, and each output signal is logically operated to perform the above-mentioned An electric wire bundle testing device comprising: a determination device including a logic operation circuit for determining the connection state of the electric wire bundle under test. 2. A logical operation circuit that sequentially uses one end and the other end of the same wire of each wire bundle as one end of the wire bundle to which timing pulses are sequentially applied, and to which the gate circuit output is applied when the pulse is applied. An electric wire bundle test according to claim 1, characterized in that the connection state of the electric wire bundle to be tested is displayed by the wire number by associating the logic operation circuit with the wire number of the electric wire. Device.