JPS627984B2 - - Google Patents

Description

[Detailed description of the invention]

When a large number of electrical conductors are bundled together (this bundle is referred to as a wire harness in this specification) and connected between devices or between circuits within a device,
It is required to use a wire harness that has been manufactured in advance as a wire harness and tested to ensure that the continuity of each conducting wire and the connection with other wires are as designed. Various methods for testing such wire harnesses have been proposed in the past. Manual testing using a tester or buzzer is simple and easy to handle;
When there are a large number of conductors, it is easy to make mistakes and is extremely inefficient. Therefore, in order to improve efficiency, tests are conducted using a computer and the results are printed out on a printer. Handling is complicated, such as when checking a small amount of harness, and inspection costs are extremely high. SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide an automatic checker that can automatically check defective wire numbers in a wire harness simply by connecting the wire harness under test to a defect detection circuit. Embodiments of the present invention shown in the drawings will be described below. FIG. 1 is a block diagram showing a configuration in which a properly wired master wire bundle is used as an embodiment of the present invention. 1 is the wire harness under test,
2 is a master wire bundle that has been wired accurately in advance; 3 is a defect detection circuit that detects disconnections and short circuits while comparing the wire harness under test 1 and the master wire bundle 2; 4;
5 is a pulse oscillator that obtains clocks for all circuits and detection pulses for the detection circuit; 5 is a decoder circuit that supplies the output pulses of the pulse oscillator 4 to the failure detection circuit as circulating pulses; and 6 is a control circuit that is the failure detection circuit 3. A disconnection and/or short circuit signal is sent to the display circuit based on a defect signal from the display circuit and a match signal from a verification circuit, which will be described later, or a pass signal is generated when no defect is detected. 7 is a counter circuit that counts according to the output of the decoder circuit 5; 8 is a latch circuit that holds the output of the counter circuit as a defective wire number (point); 9 is a display circuit; latch circuit 8
It decodes the output signal and displays the digital value, and also displays a defective state upon receiving a disconnection and/or short circuit signal. Reference numeral 10 denotes a collation circuit which collates the output signals of the counter circuit 7 and the latch circuit 8 and sends a coincidence signal to the control circuit 6 if they match. When the wire harness under test 1 and the master wire bundle 2 are arranged as shown in Fig. 1, and the checker is powered on, the counter circuit 7, latch circuit 8, and display circuit 9 are all reset, and the Pulses begin to be output. The pulses are sequentially applied in time to the defect detection circuit 3 by the decoder circuit 5, and the corresponding wire numbers of the wire harness under test 1 and the master wire bundle 2 are inspected. If a defect is detected on the way, a defect signal is sent to the control circuit 6, and the inspection circuit 3 inspects the next wire number. When the final wire number of the wire harness under test is reached,
The decoder circuit 5 applies a pulse again to the first wire number and repeats the test. This repeated operation by the decoder circuit 5 is called a scan. The counter circuit 7 receives and sequentially counts pulses whose number is equal to the wire number of the inspection circuit 3 being scanned. At the aforementioned defect location, the defect signal is sent to the control circuit 6 and then to the latch circuit 8 as a latch signal. The latch circuit 8 holds the count value of the counter circuit 7 as a defective wire number, and displays the wire number on the display circuit 9. At the same time, the control circuit 6 sends a defective state (such as a disconnection or short circuit) to the display circuit 9, so that it can also be displayed. A defective wire number other than the initially detected defective wire number is detected by the defect detection circuit 3 and a defective signal is sent to the control circuit 6, but a signal as a latch signal is not sent.
When the inspection scan of the defect detection circuit 3 completes one cycle and reaches the initial defective wire number (that is, the wire number held by the latch circuit 8), the verification circuit 10 checks the counter circuit 7.
and the latch circuit 8, and since they match, a match signal is sent to the control circuit 6. Since a coincidence signal is obtained each time a scan is performed, a timer provided in the control circuit 6 is activated by the initial coincidence signal.
Then, after a period of time has elapsed that allows the inspector to read and recognize the defective wire number in the display circuit 9, the timer is stopped, and the control circuit 6 resets the latch circuit 8 in response to a match signal from the verification circuit 10 that arrives immediately after that. Therefore, when a defective signal for the next defective wire number is applied from the detection circuit 3 to the control circuit 6, the operation of the latch circuit 8 is controlled by the counter circuit 7.
, that is, the second defective wire number, the display on the display circuit 9 is updated. The above is an example in which a timer is provided in the control circuit 6, but a counter may also be used. Since a match signal from the matching circuit 10 is obtained each time a scan is performed, the number of match signals is counted, and the counter is operated until the number of match signals arriving reaches an appropriate number. When a predetermined number has been counted, the counter of the control circuit 6 applies a reset signal to the latch circuit 8, and the display is updated by the next defect detection signal. If the defect detection circuit 3 starts operating and there is no defect, the control circuit 6 does not respond immediately after one scan, but includes the situation after repeated scans (or after confirmation three more times). Generates a pass signal. It is preferable that the pass signal generates a tremolo sound or lights up a pass lamp. A specific example of the configuration of the defect detection circuit 3 is shown below. In this specification, a disconnection refers to a defect in which terminals that should normally be connected are not connected to each other, a short circuit refers to a defect in which terminals that are not originally connected are electrically connected to each other, and incorrect wiring refers to a defect in which terminals that should normally be connected are not connected to each other. This refers to a failure in which a terminal is not connected to a terminal that should originally be connected, but is connected to another terminal, that is, a disconnection and a short circuit occur at the same time. (1) Regarding the case of disconnection failure For example, as shown in Figure 2, even though M1-M2 are connected, if m1-m2 is unwired, when S1 is applied, M1-
EX2A is “H” through the connection line of M2. Since no pulse is input to S2, EX2B is “L”, therefore EX2F is “H”, NAND3
Both A and 3B are "H", and NAND3F is "L", so the output "L" signal of B11 changes to "H" via D13, and as a result of the operation by AND1, an "H" signal is issued to the "disconnection" terminal. , it can be seen that there is an unwired defect related to the pulse terminal S1, that is, the terminal m1. If a light emitting diode and an alarm generating device are attached to the "disconnection" terminal, defects can be detected immediately and by an alarm sound. Since NAND4A is "H" and NAND4B is "L", NAND4F becomes "H" and the signal of B12 does not change. Next, when the pulse of S1 ends and a pulse is applied to S2, the NAND1
F becomes “L” and an “H” signal is obtained at the “disconnection” terminal. It can be seen that there is a disconnection defect related to the pulse terminal S2, that is, the terminal m2. As a result, in addition to the defective location in the case of S1 mentioned above, the terminal m1-m
There may be a disconnection defect between the two. (2) In case of short circuit failure For example, as shown in Figure 3, M1-M2 and M
3-M4 is connected whereas m1-m2
and m3-m4 are connected whereas m1
-m2 and m3-m4 are connected and further m2-m
3 is also connected, EX3B and EX4B are both “H” by applying a pulse to S1, EX3
A, EX4A are both "L", EX3F, EX4F are both "H", so NAND6A, EX4A are both "H",
NAND8A and 8B are both "H", NAND6
Both F and NAND8F become "L", and a "short circuit" signal is generated from B12. Therefore, it can be seen that there is a short-circuit defect related to S1, that is, terminal m1. Next, when pulses are sequentially applied to the S2, S3, and S4 terminals, a signal indicating a short-circuit failure is generated in connection with the terminals m2, m3, and m4 each time. Therefore, it is possible to detect a defect in which the terminals m1, m2, m3, and m4 are shorted to each other. Or, as shown in the terminal connection diagram in Figure 4, there is an m3-m4 connection for the wire bundle under test.
Even if there is no connection between m1 and m2 and instead there is a connection between m1 and m3, if pulses are applied sequentially from S1 in the same way as described above, there will be a "miswiring" in relation to m1, a "disconnection" in m2, and a "short circuit" in m3. A signal is generated, allowing you to know if there is a defect. (3) In the case of faulty wiring For example, as shown in Figure 5, if M1 and M2 are connected, but m1 and m2 are not connected and m1 and m3 are connected, the connection goes to S1. EX2A “H”, EX2B “L” by applying the pulse of
Therefore, EX2F is "H", and both NAND3A and 3B are "H", and NAND3F is "L", so the output of B11 is "H". EX3 at the same time
EX3F “H” because A “L”, EX3B “H”
Therefore, both NAND6A and NAND6B are “H”,
Since NAND6F is "L", the output of B12 is "H". Therefore, since each output of B11 and B12 is both "H", the "miswiring" terminal is "H".
(The "disconnection" and "short circuit" terminals remain at "L"). Therefore, it can be seen that there is a wiring error related to S1, that is, terminal m1. Next, when S2 is applied, NAND1F becomes "L" and a "broken wire" defect is displayed in relation to S2, that is, terminal m2. Then, when S3 is applied, NAND2F goes “L”
Therefore, there is a "short circuit" related to S3, that is, terminal m3.
A defect is displayed. Therefore, it can be determined that the wiring that should be connected from m1 to m2 is incorrectly wired from m1 to m3. (4) Relationships from (1) to (3) above The respective outputs of the NC terminal and SH terminal in Figs. 2 to 5 are processed appropriately in the control circuit 6 in Fig. 1, and the signals “L” and “H” are By displaying these in combination, it is possible to accurately display the defective state.

[Table] The above describes the case of detecting defects using a master wire bundle, but by changing the configuration of the defect detection circuit as shown in Figure 6, it is possible to detect defects only in the wire harness under test. can. In Fig. 6, the same reference numerals in Figs. 2 to 5 indicate the same things, INV1, INV2... INVn is an inverter, 1A, 1B are terminals on both sides of wire number 1, 2A,
2B is a terminal on both sides of wire number 2. The S terminal is connected to the A terminal of the wire that is connected to another connection line, and the S terminals are connected to each other. Further, FF1 and FF2 indicate flip-flops, and L1 and L2 indicate display lamps. At the same time as the power switch is turned on, a scan is repeated from wire number 1 to the final wire number at a fast cycle to ensure continuity in wire number 1, short circuit between wire number 1 and other wire numbers, continuity between wire number 2, and short circuit between wire number 2 and other wire numbers. Inspect in the order of short circuits with wire numbers. The disconnection signal/short circuit signal is displayed via INV and FF. The data selector DSL is terminal 1.
B, 2B...... are connected to terminal Z in sequence. Now, a test to determine whether the first wire is short-circuited with other wires will be explained. When the signal at the pulse terminal becomes "H", the output of EX11 in the first line gate circuit becomes "L" and the output of NAND11 becomes "H", but is blocked by D11. Since all the terminals after the pulse terminal are "L", the outputs of NAND11 to NAND1n are also all "H", but
blocked by D12 to D1n, the lamp L2
does not light up. Terminal NC remains at "L".
In addition, when the first wire 1A and the second wire 2A are short-circuited, the output of NAND11 is "H" as in the case of no short-circuit.
However, "H" is input to one side and "L" to the other input terminal of EX12 through the 2A terminal, and EX1
At the same time, the output of NAND12 becomes "H", the output of NAND12 becomes "L", that is, the input side of INV21 through D12 becomes "L", the D terminal of FF1 becomes "H", the terminal becomes "L", and the short circuit lamp is activated. Turn on L1 and connect the terminal
Output “H” to SH. In this way, according to the present invention, when the output pulses of the pulse oscillator are circulated and applied to the wire harness defect detection circuit, defects in the wire harness under test are automatically detected without the inspector having to operate the device each time. It is extremely convenient because it displays whether the wire is good or bad, and if it is defective, the wire number can be immediately known, and if the defect detection circuit is configured to notify the defective state, repairs can be started immediately after seeing the display circuit. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 to 5 are diagrams showing specific configuration examples of the defect detection circuit in FIG. 1, and FIG. 6 is a block diagram showing the configuration of the defect detection circuit in FIG. 1. FIG. 3 is a diagram showing another example of the circuit. DESCRIPTION OF SYMBOLS 1... Wire harness under test, 2... Master wire bundle, 3... Defective detection circuit, 4... Pulse oscillator, 5... Decoder circuit, 6... Control circuit, 7...
... Counter circuit, 8 ... Latch circuit, 9 ... Display circuit, 10 ... Verification circuit, M1, M2, ... Master wire bundle connection terminal, m1, m2, ... Wire harness connection terminal under test, S1, S2 , ... Circulating pulse application terminal, EX1, EX2, ... Exclusive OR gate, NAND1, NAND2, ... NAND gate,
B1, B2,...B11, B12,...Buffer amplifier.

Claims (1)

[Scope of Claims] 1. A wire harness defect detection circuit, a pulse generator, a decoder circuit that distributes the pulse generator output to the wire harness defect detection circuit, and a counter that counts the pulse generator output. A latch circuit that holds the counter output in response to a failure detection signal from the failure detection circuit, and a display circuit that displays the output of the latch circuit, the output of the latch circuit receiving the initial detection signal from the failure detection circuit. An automatic wire harness checker characterized by displaying defective wire numbers. 2. A control circuit for a defect detection circuit, a decoder circuit, a latch circuit, etc. is provided, the defect detection circuit is configured to be able to send a defect status to the control circuit, and the control circuit causes the display circuit to display the defect status; A patent characterized in that a plurality of defective wire numbers and states are sequentially displayed by prohibiting the second and subsequent detection signals from the defect detection circuit from being input as latch signals to the latch circuit for a predetermined period of time. An automatic wire harness checker according to claim 1. 3. A verification circuit is provided to detect the coincidence between the counter and the latch circuit output, the timer is activated by the initial coincidence signal, and the latch circuit is reset by the coincidence signal after a predetermined period of time has elapsed.
3. The wire harness automatic checker according to claim 2, wherein the wire harness automatic checker displays the status sequentially. 4. A matching circuit is provided to detect the matching state between the counter and the latch circuit output, and the number of arriving matching signals is counted from the initial matching signal, and the latch circuit is reset by the matching signal a predetermined number of times.
3. The wire harness automatic checker according to claim 2, wherein the wire harness automatic checker displays the status sequentially.