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JPS6155780B2 - - Google Patents
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JPS6155780B2 - - Google Patents

Info

Publication number
JPS6155780B2
JPS6155780B2 JP54105019A JP10501979A JPS6155780B2 JP S6155780 B2 JPS6155780 B2 JP S6155780B2 JP 54105019 A JP54105019 A JP 54105019A JP 10501979 A JP10501979 A JP 10501979A JP S6155780 B2 JPS6155780 B2 JP S6155780B2
Authority
JP
Japan
Prior art keywords
electrode
ohmic
layer
forming
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54105019A
Other languages
Japanese (ja)
Other versions
JPS5629340A (en
Inventor
Hirohisa Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP10501979A priority Critical patent/JPS5629340A/en
Publication of JPS5629340A publication Critical patent/JPS5629340A/en
Publication of JPS6155780B2 publication Critical patent/JPS6155780B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07336Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07337Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy

Landscapes

  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 この発明は半導体素子の電極形成方法にかか
り、特に―族化合物半導体素子における金を
主成分とする電極の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming an electrode of a semiconductor device, and particularly to a method of forming an electrode containing gold as a main component in a - group compound semiconductor device.

この分野においては、―族化合物半導体基
板の表面に形成される金属電極は一般にこの基板
とのオーミツク性およびAuボンデイングワイヤ
とのボンデイング性を考慮して、例えばAuBe,
AuSiの如き金合金層を用いて構成されている。
In this field, metal electrodes formed on the surface of - group compound semiconductor substrates are generally made of metal electrodes such as AuBe,
It is constructed using a gold alloy layer such as AuSi.

ところで、上記オーミツク性をより高めるため
に熱処理を施すことがあるが、この場合、その反
面では金合金層とボンデイングワイヤとの間のボ
ンデイング強度の低下を生じている。
Incidentally, heat treatment is sometimes performed to further enhance the ohmic properties, but in this case, on the other hand, the bonding strength between the gold alloy layer and the bonding wire is reduced.

また、このボンデイング強度を改善しようとし
てボンデイングワイヤと同質の金層をさらに上記
合金層に積層し、この金層にボンデイングワイヤ
をボンデイングすることもあるが、それでもなお
このボンデイング強度が充分に改善されていな
い。
In addition, in an attempt to improve this bonding strength, a gold layer of the same quality as the bonding wire is sometimes further laminated on the alloy layer, and the bonding wire is bonded to this gold layer, but the bonding strength is still not sufficiently improved. do not have.

叙上の状況の中で、本発明者がこのような問題
の原因を調べてみたところ、上記熱処理において
金合金層と半導体基板とのオーミツク性は改善さ
れているものの、半導体基板の構成成分、または
金合金層のオーミツク成分が電極膜の表面にまで
拡散し表層に薄い酸化層を形成していることに起
因して、前者の場合はワイヤと金合金層との界面
でのボンデイング性が阻害され、後者の場合は金
層と金合金層との界面でのボンデイング性を阻害
していることが判つた。
Under the circumstances described above, the present inventor investigated the cause of such problems and found that although the ohmic properties between the gold alloy layer and the semiconductor substrate were improved in the above heat treatment, the constituent components of the semiconductor substrate, Or, in the former case, bonding properties at the interface between the wire and the gold alloy layer are inhibited due to the ohmic components of the gold alloy layer diffusing to the surface of the electrode film and forming a thin oxide layer on the surface layer. It was found that in the latter case, bonding properties at the interface between the gold layer and the gold alloy layer were inhibited.

本発明の目的は、熱処理によるオーミツク性を
改善するとともに、この熱処理に起因するボンデ
イング性の阻害を避けてボンデイング性をも改善
するところにある。
An object of the present invention is to improve the ohmic properties due to heat treatment, and also to improve the bonding properties by avoiding the inhibition of bonding properties caused by this heat treatment.

本発明は、―族化合物半導体単結晶基板上
に金合金層を被着して熱処理を施すことにより前
記基板に対しオーミツク接触するオーミツク電極
を形成する工程と、前記熱処理に当つて生じた前
記オーミツク電極の露出表層をエツチング除去す
る工程と、その後前記オーミツク電極に積層して
金層を被着することによりボンデイング電極を形
成する工程とを具備してなる半導体素子の電極形
成方法であり、オーミツク性とボンデイング性の
双方の向上が得られる。
The present invention provides a step of forming an ohmic electrode in ohmic contact with the substrate by depositing a gold alloy layer on a - group compound semiconductor single crystal substrate and performing heat treatment, and a step of forming an ohmic electrode in ohmic contact with the substrate, and removing the ohmic electrode produced during the heat treatment. A method for forming an electrode for a semiconductor device, which comprises a step of etching away the exposed surface layer of the electrode, and a step of forming a bonding electrode by laminating and depositing a gold layer on the ohmic electrode. and bonding properties can be improved.

以下に、本発明の一実施例につき図面を参照し
て説明する。
An embodiment of the present invention will be described below with reference to the drawings.

一例のGaP発光ダイオードの製造において、第
1図に示す如くGaP基板1が一方の主面にN型領
域1nを、他方の主面にP型領域1pを夫々露出
し、基板内にPN接合1pnを有しており、そのP
型結晶およびN型結晶の各露出面にオーミツク電
極としてのAuBe合金層、AuSi合金層2を真空蒸
着する。次に、N2ガス中で520℃、5分間熱処理
を施し、オーミツク電極と基板露出面とのオーミ
ツク接触を得ているが、この際生じたオーミツク
電極2′(第2図)の露出表面のBe,Gaの酸化物
層3を除去するために、このGaP基板を塩酸中に
て煮沸程度の加熱を10分間施したのち、充分に純
水洗浄して乾燥させる(第3図)。次に、P型オ
ーミツク電極上にAu層4を真空蒸着し、写真蝕
刻技術を用いて所定の電極パターンに形成する
(第4図)。
In manufacturing an example of a GaP light emitting diode, as shown in FIG. 1, a GaP substrate 1 has an N-type region 1n exposed on one main surface and a P-type region 1p on the other main surface, and a PN junction 1pn is formed in the substrate. and its P
An AuBe alloy layer and an AuSi alloy layer 2 as ohmic electrodes are vacuum-deposited on each exposed surface of the type crystal and the N-type crystal. Next, heat treatment was performed at 520°C for 5 minutes in N2 gas to obtain ohmic contact between the ohmic electrode and the exposed surface of the substrate. In order to remove the Be and Ga oxide layers 3, this GaP substrate is heated to boiling level in hydrochloric acid for 10 minutes, then thoroughly washed with pure water and dried (Figure 3). Next, an Au layer 4 is vacuum deposited on the P-type ohmic electrode and formed into a predetermined electrode pattern using photolithography (FIG. 4).

叙上の本発明方法によれば、オーミツク電極の
表層に基板とのオーミツク性を高めることができ
る上に、オーミツク電極の表層に生じた酸化物の
層を除去してボンデイング電極を形成するのでオ
ーミツク電極とボンデイング電極との接着性が高
く形成される。
According to the method of the present invention described above, it is possible to improve the ohmic properties between the surface layer of the ohmic electrode and the substrate, and the oxide layer formed on the surface layer of the ohmic electrode is removed to form a bonding electrode. The electrode and the bonding electrode are formed with high adhesiveness.

このため、ボンデイング能率と歩留が著るしく
向上し、例えば全自動ボンダーを使用した場合、
従来は歩留りが95〜99%のようにバラツキも大き
いだけでなく、平均的に歩留りが低かつたのに比
較して本発明によれば、常に99.99%の歩留りが
確保され、製品の製造能率と歩留に顕著な向上を
示した。
This significantly improves bonding efficiency and yield, for example when using a fully automatic bonder.
In the past, the yield not only varied widely, such as 95-99%, but also had a low average yield, but with the present invention, a yield of 99.99% is always ensured, improving product manufacturing efficiency. This showed a remarkable improvement in yield.

なお、本発明におけるオーミツク電極のエツチ
ヤントは塩酸に限られず、他の鉱酸、界面活性剤
等によつてもよいことは言うまでもない。
It goes without saying that the etchant for the ohmic electrode in the present invention is not limited to hydrochloric acid, but may also be other mineral acids, surfactants, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第4図はGaP発光ダイオードの製
造工程の一部を示す素子の一部の断面図である。 ……GaP基板、1p……GaP基板のP領域、
2′……オーミツク電極、3……オーミツク電極
表層の酸化物層、4……ボンデイング電極。
FIGS. 1 to 4 are cross-sectional views of a part of a GaP light emitting diode, showing a part of the manufacturing process of the device. 1 ...GaP substrate, 1p...P region of GaP substrate,
2'... Ohmic electrode, 3... Oxide layer on the surface of the Ohmic electrode, 4... Bonding electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 ―族化合物半導体単結晶基板上に金合金
層を被着して熱処理を施すことにより前記基板に
対しオーミツク接触するオーミツク電極を形成す
る工程と、前記熱処理に当つて生じる前記オーミ
ツク電極の露出表層の酸化物層をエツチング除去
する工程と、その後前記オーミツク電極に積層し
て金層を被着することによりボンデイング電極を
形成する工程とを具備してなる半導体素子の電極
形成方法。
A step of forming an ohmic electrode in ohmic contact with the substrate by depositing a gold alloy layer on a 1- group compound semiconductor single crystal substrate and performing heat treatment, and an exposed surface layer of the ohmic electrode that occurs during the heat treatment. 1. A method for forming an electrode for a semiconductor device, comprising the steps of etching away the oxide layer of the oxide layer, and then forming a bonding electrode by laminating the ohmic electrode with a gold layer.
JP10501979A 1979-08-20 1979-08-20 Formation of electrode on semiconductor element Granted JPS5629340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10501979A JPS5629340A (en) 1979-08-20 1979-08-20 Formation of electrode on semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10501979A JPS5629340A (en) 1979-08-20 1979-08-20 Formation of electrode on semiconductor element

Publications (2)

Publication Number Publication Date
JPS5629340A JPS5629340A (en) 1981-03-24
JPS6155780B2 true JPS6155780B2 (en) 1986-11-29

Family

ID=14396341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10501979A Granted JPS5629340A (en) 1979-08-20 1979-08-20 Formation of electrode on semiconductor element

Country Status (1)

Country Link
JP (1) JPS5629340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320282U (en) * 1986-07-18 1988-02-10

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5867078A (en) * 1981-10-19 1983-04-21 Toshiba Corp Manufacture of compound semiconductor device
KR100215338B1 (en) * 1991-03-06 1999-08-16 가나이 쓰도무 Manufacturing Method of Semiconductor Device
JP2008140811A (en) * 2006-11-30 2008-06-19 Victor Co Of Japan Ltd Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6320282U (en) * 1986-07-18 1988-02-10

Also Published As

Publication number Publication date
JPS5629340A (en) 1981-03-24

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