JPS6156648B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having a field effect transistor and operating at low power and high speed.
When configuring a logic circuit using junction type or short field effect transistors (hereinafter referred to as FETs), normally off type field effect transistors (hereinafter referred to as FETs) are usually used to simplify the circuit configuration.
(normally off) type transistors are used. However, when applying a forward voltage to the gate of an FET that is in a cut-off state due to the channel being completely pinched off at zero gate bias to turn it into a conductive state, the capacitance between the electrodes tends to increase, and overcurrent is applied to the gate. It has drawbacks such as a small logic voltage amplitude that can be applied without flowing.

An object of the present invention is to apply a reverse voltage to the gate of a normally-on FET, eliminate the need to neutralize excess minority carriers during switching, and increase the logic voltage amplitude in a high-speed semiconductor device. The purpose is to provide integrated circuits.

The present invention will be explained in detail below using the drawings.

Figure 1 shows an example of a basic circuit configuration in which the FET gate operates with a reverse voltage and can be directly connected to the next stage.

FIG. 1 is an example of a circuit configuration that simultaneously includes two-input NOR and OR gates. Figure 1 a shows the n channel.
3 FETs (T ₁ , T ₂ , T ₃ ), P channel FET
Two (T ₄ , T ₅ ) are used, and a positive voltage power supply V _D1 and a negative voltage power supply V _D2 are used. Five other resistors (R ₁ to R ₅ ) are incorporated. On the other hand, in Fig. 1b, two n-channel FETs (T ₆ , T ₇ ), p-channel FETs (T ₈ , T ₉ ), four resistors (R ₆ to R ₉ ), a positive voltage power supply V _D1 and a negative voltage Power supply V _D2 is used. All FETs used here are normally-on type FETs. Although the Vref generation circuit is not shown, it can be easily constructed using a configuration used in ECL (Emitter Coupled Logic) using bipolar transistors. The operation will be explained using FIG. 1b as an example. For example, V _D1 =+
5V, V _D2 = -5V. For example, the high level V _H of the logic level is -2V, and the low level V _L is -5V. When there is no input to FET T ₆ and T ₇ , that is, when A and B are both at level V _L ,
Both T ₆ and T ₇ are in a blocked state. Since the gate of FET T ₈ is at ground potential, T ₈ is set to be in a conductive state and Vref of T ₉ is set to be in its blocked state. Since T ₈ is conduction and T ₉ is interruption,
By setting the resistance value to a desired value, it is possible to set the NOR output terminal voltage to -2V and the OR output terminal voltage to -5V. When there is an input to either A or B or both (A or B or both become V _H = -2V),
Since either or both of T ₆ and T ₇ conduct, and the gate bias of T ₈ becomes positive and deep (reverse bias makes it deep), T ₈ is cut off. At this time, T ₉ is
Vref is set so that it changes to a conductive state.
At this time, the NOR output terminal voltage changes to -5V and the OR output terminal voltage changes to -2V. In this way, input,
Since the output voltage values can be matched, this basic circuit configuration can be directly connected to the next stage, and in this example, the logic voltage amplitude is 3V. The gates of all FETs that contribute to switching are switched with reverse voltage, and the interelectrode capacitance is small and no minority carrier injection occurs at all, so excessive minority carriers are prevented by input/output circuits during switching. No need for neutralization,
It performs high-speed operation, with the characteristics of FETs appearing as they are in operation. The operation in FIG. 1a is almost the same.

Although FIG. 1 shows a basic circuit that includes NOR and OR gates at the same time, it is not always necessary to include both. An example of the basic circuit configuration in the case of two inputs using only NOR gates and OR gates is shown in FIGS. 2a and 2b. _T10 , _T11
The NOR gate of FIG. 2a, in which the drain of T 12 and the source of T ₁₂ are held at a constant potential, is particularly suitable for high speed operation. The operations in FIGS. 2a and 2b can be easily inferred from what has been described above with respect to FIG. 1b.
T ₁₀ , T ₁₁ , T ₁₃ , T ₁₄ are n channel normal
On-type FETs T ₁₂ and T ₁₃ are p-channel normally on-type FETs, R ₁₀ to _{R 14} are resistors, V _D1 is a positive voltage power supply, and V _D2 is a negative voltage power supply.

To make the logic voltage level positive, for example, as shown in Figure 3, connect a p-channel normal voltage to the input side.
An on-type FET may be placed on the output side, and an n-channel normally on-type FET may be placed on the output side. _T16 , _T17
is a p-channel normally-on FET, T ₁₈ ,
_T19 is an n-channel normally on type FET,
R ₁₅ to R ₁₈ are resistances. Although the polarity of the voltage is reversed, the operation is almost the same as in the case shown in Fig. 1b. For example, if V _D1 = +5V and V _D2 = -5V, V _H = +
The potential can be set as 5V, V _L = +2V.

In the circuit configuration examples shown in FIGS. 1 to 3, when the number of fan-ins increases, the gate potential of the output side FET varies depending on the number of inputs, resulting in a disadvantage that the output level varies. In order to keep the output level constant regardless of the fan-in number, the output side
Just connect a constant voltage device to the gate of the FET. Constant voltage devices include Schottky diodes and SITs with gates and drains directly connected. A Schottky diode can hardly change the voltage it keeps constant, but a constant voltage SIT can greatly change the voltage it keeps constant depending on its structure. constant voltage
FIG. 4 shows an example of a circuit configuration in which the number of fan-ins is increased by inserting a SIT. An n-channel constant voltage SIT is inserted between the gate ground point of _T8 . Of course, it is not limited to this method. Also, all loads are shown as resistance, but
It goes without saying that FETs may be used, and the operating speed, noise margin, etc. are improved.

The material of the FET used in the present invention is not limited to Si, and FETs using other materials such as Ge, GaAs, and InP may be used.

All logic circuits can be constructed by combining the basic circuits of the present invention.

N-channel and p-channel FETs of the present invention
Logic circuits containing contribute to switching
The gate of the FET is free from forward voltage over all operating conditions, the logic voltage amplitude can be set arbitrarily, the capacitance between each electrode is small, and there is no minority carrier accumulation effect, so the input - There is no need to neutralize excess minority carriers by the output circuit, and the conversion conductance is large, allowing high-speed operation, and its industrial value is high.

[Brief explanation of the drawing]

1 to 4 are examples of basic circuit configurations of the present invention.

Claims (1)

[Claims] 1. An input circuit including a first normally-on field effect transistor of one conductivity type to which a non-forward-biased input signal of one polarity is applied to at least the gate, and power is supplied to the input circuit. an output circuit including at least a second normally-on field effect transistor of the other conductivity type, and a power source of one polarity for supplying power to the output circuit; 1. A semiconductor integrated circuit characterized in that signal transmission is performed by supplying an output signal of the other polarity of the circuit to the output circuit, and neutralization of excess minority carriers is not required at the time of switching. 2. The input circuit and the output circuit have a common potential point, and the first normally-on field-effect transistor and the second normally-on field-effect transistor are directly or otherwise connected to the common potential point. The semiconductor integrated circuit according to claim 1, characterized in that the semiconductor integrated circuit has a source or a drain connected through an element. 3. The semiconductor according to claim 2, wherein the input circuit includes a constant voltage element connected between the first normally-on field effect transistor and the common potential point. integrated circuit. 4. The input circuit has at least one other normally-on field effect transistor having one conductivity type and connected in parallel with the first normally-on field effect transistor.
Claims 1 to 3 include an on-type field effect transistor and a plurality of input terminals connected to the gates of the first and other normally on-type field effect transistors. The semiconductor integrated circuit according to any one of the above.