JPS6156664B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a type of facsimile receiver that performs recording by moving a recording head having a plurality of elements aligned in the sub-scanning direction in the main scanning direction.

In the facsimile receiver as mentioned above, since the recording head scans a plurality of lines (for example, n) lines at a time, the image signals transmitted from the transmitting side are sequentially stored in the memory, and the image signals for n lines are stored. At that point, the image signals for those n lines are recorded all at once. This situation is shown in FIG. 1, where H is a recording head having n recording elements P ₁ , P ₂ . . . _Po , and K is recording paper.

By the way, in addition to the image signal mentioned above, control signals such as the EOM signal indicating the end of the image signal and the PIS signal indicating the interruption of transmission/reception are transmitted from the transmitting side, and sometimes noise is also received when the line is momentarily interrupted. . At that time, even if a signal other than such an image signal is received,
It takes several lines of time to confirm this, and therefore, during that time, the previous control signal and the like are stored in the memory following the image signal. For this reason, if the signal read from the memory is directly guided to the recording head for recording, there will be a problem that unnecessary signals will be recorded over several lines.

Therefore, we propose a facsimile receiver that eliminates the drawbacks of the present invention, and the details thereof will be explained below with reference to the drawings.

FIG. 2 shows a schematic configuration of a facsimile receiver according to the present invention. In the figure, 1 is a received signal demodulation circuit, and the signal demodulated by this circuit is guided to first and second memory circuits 3 and 4 via an AND gate 2.

In each of the first and second memory circuits 3 and 4, signals from the demodulation circuit 1 are written alternately for n lines (n is the number of elements of the recording head, which will be described later).
It consists of a RAM, and when one of them is written, the other is controlled to be in a read state. The control circuit 5 composed of a microprocessor is responsible for switching the memory every n lines and detecting the EOM and PIS signals.

On the other hand, 6 is an image signal carrier detection circuit, which detects for each line whether or not an image signal carrier exists in the received signal introduced into the demodulation circuit 1, and thereby Determine whether the received signal is an image signal. At this time, this image signal carrier detection operation is performed during the phase signal period preceding the image information of each line.

Then, the detection circuit 6 outputs a signal of "1" (high level) for the line determined to be an image signal, and a signal of "0" (low level) for the line determined not to be an image signal. .

Now, for example, if the received signals for n lines are all image signals, since the AND gate 2 is opened by the output of the detection circuit 6, each image signal is sent to the first memory circuit. Therefore, the contents of this first memory circuit are as shown in FIG. Then, this content (image signal) is read out during the next writing to the second memory circuit 4 and is derived via the multiplexer 7.

Here, L ₁ , L ₂ . . _{. Lo} in the column direction in Fig. 3 represents each line, and A ₁ , A _{2 .} The number of bits of the fractional signal is m), and the reading of the first and second memory circuits 3 and 4 is performed column by column (n bits each) from the first column to the m-th column by the control circuit 5. It is becoming more and more practiced.

Note that, as described above, the first and second memory circuits 3 and 4
In the present invention, reading out signals written in row (line) units in FIGS. 3 and 4 in column units is referred to as orthogonal transformation.

In this way, each n-bit image signal from the multiplexer 7 is stored in the shift register 8. Then, when each of the n bits is stored, the image signals derived from the register 8 in parallel are applied to the n elements (see FIG. 1) of the recording head 10 through the drive circuit 9. .

Therefore, every time an n-bit image signal is stored in the shift register 8, the n-bit image signal is recorded at once in the sub-scanning direction. At that time, readout in column units from the first and second memory circuits 3 and 4 is as follows:
Since this is carried out in synchronization with the movement of the head H in the main scanning direction, recording of n lines is completed by one main scanning. In the case of FIG. 3, the image signal is recorded over all of the n lines.

Next, when recording the image signal from the second memory circuit 4 (this is done in the same manner as described above), the demodulation circuit 1
The signals for the next n lines are led to the first memory circuit 3 via the AND gate 2, but at that time,
Of the signals for n lines, up to the i-th line is an image signal, and the (i+1)th line to (n-2)th line
It is assumed that the EOM signal up to the first line is the above-mentioned EOM signal, and after that the communication ends and there is no signal.
Then, since the AND gate 2 is closed after the (n-2)th line, the "0" signal that is the output of this AND gate is transmitted from the (i+1)th line of the first memory circuit 3. It will be written down. At this time, the control circuit 5 controls the writing of this "0" signal so that it continues to be performed even after the (n-2)th line where the received signal is in a non-signal state. That is, this control circuit 5
When an EOM or PIS signal is detected, writing continues for at least n lines from the start of detection. Therefore, in this case, the contents written in the first memory circuit 3 are as shown in FIG.

Note that when an image signal is derived again after noise appears temporarily from the demodulation circuit 1, the previous "0" signal is written only for the line where the noise appeared.

Now, when the first memory circuit 3 enters the read state again and the signal shown in FIG. ) bit to n-th bit are all "0" signals. and,
This signal is introduced into the shift register 8, and thereafter the recording operation is performed in the same manner as described above.

Now, assuming that the image signal is binarized with black information as "1" and white information as "0", up to the i-th line among the n lines recorded in this case, The image signal in the first memory circuit 3 is recorded as is, but from the (i+1)th line onwards, a white signal as non-trivial information is always recorded. Therefore, unnecessary signals such as the EOM signal and noise derived from the demodulation circuit 1 are not recorded.

Note that if the image signal is binarized with the black information as "0" and the white information as "1", the signal format of the output of the image signal carrier detection circuit 6 is reversed, and the AND gate 2 is Just replace it with OR gate.

Since the facsimile receiver of the present invention is configured as described above, unnecessary signals such as control signals received following the image signal and noises received due to instantaneous line interruptions are not recorded. There is no problem,
Therefore, it is an excellent facsimile receiver of the type that records n lines at a time.

[Brief explanation of the drawing]

The drawings relate to the present invention; FIG. 1 is a diagram schematically showing its recording operation, FIG. 2 is a block diagram showing a schematic configuration of its main parts, and FIGS. 3 and 4 are diagrams explaining its operation. This is a diagram for H: Recording head, K: Recording paper.

Claims (1)

[Claims] 1. Image signals for n lines are recorded at once by moving a recording head having n (n≧2) elements aligned in the sub-scanning direction in the main scanning direction. This is a facsimile receiver configured to transmit data, which includes: (a) memory means for storing received signals for each n line; and (b) determining whether or not the received signal is an image signal line by line. (c) For a line that is determined to be an image signal by the means described in (b) above, the image signal is written into the memory means, and when it is determined that it is not an image signal, an unnatural signal is written to the memory means at least for the line. (d) means for guiding a signal read out after orthogonal transformation from the memory means to the recording head. 2. If a signal other than the image signal is detected by the means described in (b) above, and that signal is a predetermined signal, the means described in (c) above thereafter records the random signal up to the final address of the memory means. The facsimile receiver according to claim 1, wherein the facsimile receiver is controlled to write. 3. The means described in (b) above is configured to perform the above-mentioned determination operation by detecting the image signal carrier in the received signal. Facsimile receiver as described in section.