JPS6156901B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer device for a camera power supply, and particularly to a compensation circuit thereof.

2. Description of the Related Art Cameras whose power switch is turned on in conjunction with a shutter button are known to have a timer device for supplying power to a load such as an exposure meter for a certain period of time even after the shutter button is released. This timer, which operates for a certain period of time, is provided based on the consideration that the aperture, distance ring, etc. can be adjusted even if the shutter button is released. One possible method for measuring a certain period of time after the shutter button is released is to count the clock pulses with a digital counter until a predetermined count value is reached. In a timer circuit that uses such a digital counter to turn off the power after a certain period of time, when the power is cut off and the power supply voltage decreases, the logic state may become unstable and the power may be turned on again. It was hot.
Therefore, the power is not turned off after a predetermined period of time, resulting in excessive power consumption, which is inconvenient in terms of power saving.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a power-off timer circuit that can reliably turn off the power.

FIG. 1 shows an embodiment of the present invention. A switching transistor is connected between the primary power supply line 10 containing the power source E ₀ and the secondary power supply line 20 containing the load L.
Tr ₅ is inserted. In this embodiment, the load L is a light meter. The base circuit of the transistor _Tr5 is grounded via a resistor _R6 , a diode _D2 and a switch S. When switch S is closed, transistor Tr ₅ turns on and outputs to secondary line 20.
E ₁ is occurring. On the other hand, the base potential of the transistor Tr ₁ is grounded via the diodes D ₃ and D ₁ , so the transistor Tr ₁ is turned off, and the reset voltage from the collector load R ₁ becomes High, and the flip-flops FF ₁ to _{FF o+1} are reset. Tori _o+1
Output is High. flipflop FF~
The counter consisting of FF _o+1 does not count clock pulses from the oscillator DSC while it is being reset.
_o+1 is maintained High. _o+1 output is resistor
Since the base circuit of the transistor Tr ₂ is energized via R ₃ , the transistor Tr ₂ is turned on at this time, so the transistor Tr ₃ is turned off and the transistor Tr ₄ is turned on. When the switch S is closed in this way, Tr ₄ is turned on and connected in parallel with the switch S circuit, so even if the switch S is opened, the transistor Tr ₅ is maintained in the ON state. Here diode D ₂ is connected to transistor Tr ₄ through diode D ₃
This is to prevent current from flowing.

When switch S opens, Tr ₁ turns ON.
Therefore, the reset output becomes Low and the counter consisting of flip-flops FF ₁ to _{F o +1} becomes the oscillator OSC.
Start counting clock pulses from . During this counting, _{the o +1 output of FF o} +1 is High, so the transistor Tr ₅ is turned on and outputs the output voltage E ₁ to the secondary line 20. After a certain period of time, _{the o+1} output of flip-flop FF _o +1 becomes
When the logic state changes from High to Low, the states of the transistors Tr ₂ to Tr ₅ change, the transistor Tr ₅ is switched off, and the output voltage E ₁ becomes zero.

Regarding this operation, first consider the case where there is no capacitor C. Flip-flop after a predetermined time
When the o _{+1 output of FF o +1} goes low, the transistor
Tr ₂ is turned OFF. Thereby transistor Tr ₃
is ON, transistors Tr ₄ and Tr ₅ are OFF, and the secondary line is disconnected from the power supply E ₀ . The transient state of this operation will be explained in detail. Transistor Tr ₅ is OFF
When the output voltage E ₁ decreases, the collector voltage and base voltage of the transistor Tr ₃ decrease at the same time, which increases the ON resistance of the transistor Tr ₃ and turns off the transistors Tr ₄ and Tr ₅ sufficiently.
become unable. Due to this action, the output voltage E ₁ does not suddenly become zero, but is maintained as an unstable output voltage E ₁ for a certain period of time until it is completely cut off and becomes zero. In this state, the counter is supplied with power from the secondary line, so flip-flops FF ₁ to _{F o+1} are likely to malfunction, and _o+1 is
It may go from Low to High, in which case transistor Tr ₂ is turned on and transistor Tr ₃ is turned off, resulting in transistors Tr ₄ and Tr ₅ being turned on again.

Therefore, even if the output voltage E ₁ decreases, the ON state of the transistor Tr ₃ is maintained completely, and the ON resistance of the transistor Tr ₃ accompanying the decrease in the output voltage E ₁ is made sufficiently low, and the ON state of the transistor Tr ₄ is turned OFF. By not affecting the state, the output voltage E ₁
It is necessary to cut sharply. To this end, the present invention includes a capacitor C as a compensation circuit in the base circuit of the transistor Tr ₃ to maintain the output voltage E ₁ during operation for a certain period of time. One terminal of the capacitor C is connected to the secondary line 20 via a diode D4 as shown in Fig. 1, and the intersection of the capacitor C and _the diode _D4 is connected to the base of the transistor _Tr3 via a resistor _R4 . ing. Further, the other terminal of capacitor C is grounded. In operation, capacitor C is a diode
It is charged to the output voltage _E1 via _D4 . Even if the output voltage _E1 decreases in the above operation after the power switch S is turned off, the charge stored in the capacitor C supplies the base current of the transistor _Tr3 and keeps the transistor _Tr3 completely turned on. do.
As a result, the transistors Tr ₄ and T ₅ are completely turned off, and the secondary line is quickly disconnected from the power source E ₀ . Therefore, it is possible to eliminate the influence of malfunction of the counter due to transient fluctuations in the secondary line during cutting.

[Brief explanation of the drawing]

The figure is a circuit diagram according to an embodiment of the present invention. [Explanation of symbols of main parts], Primary line...1
0, Secondary line...20, First transistor switch...Tr ₅ , Second transistor switch...
... _Tr2 , _Tr3 , _Tr4 , power switch...S, counter... _FF1 to FF _o+1 .

Claims (1)

[Claims] 1 A primary power supply line including a power source, a secondary power supply line including a load, a first transistor switch inserted between the primary and secondary lines, and turns on the first transistor switch when closed. a counter powered from the secondary line which is reset when the power switch is closed and which counts clock pulses when it is open and generates a timer output after a count corresponding to a predetermined time; a second transistor switch connected in parallel to the power switch and supplied with power from the secondary line, which is turned ON when no timer output is generated from the counter and turned OFF when a timer output is generated; The secondary line voltage is charged until the timer output is generated.
A timer device for a camera power supply comprising a capacitor connected so that the charged charge becomes an energizing current that maintains the OFF state of the second transistor switch after the timer output.